NEC PD78214 - Manual (Page 395)

366
µ
PD78214 Sub-Series
Fig. 13-17 Timing When External Wait Signal Is Used
(a) Read timing
Higher address
Lower
address
(output) Data (input)
Hi-Z Hi-Z
A8-A15
(output)
AD0-AD7
ASTB (output)
RD (output)
f CLK
Note
WAIT (input)
(b) Write timing
Higher address
Lower
address
Data
Hi-Z Hi-Z
A8-A15
(output)
AD0-AD7
(output)
ASTB (output)
WR (output)
f CLK
Note
WAIT (input)
Note f
CLK
: System clock frequency (f
XX
/2)