Renesas SH7641 - Manual (Page 88)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 38 of 982
REJ09B0023-0400
Table 2.3 Source Register in DSP Operations
Guard Bits Register Bits
Registers Instructions 39 32 31 16 15 0
A0, A1 DSP Fixed-point, PDMSB,
PSHA 40-bit data
Integer 24-bit data
Logical, PSHL, PMULS 16-bit data
MOVX/Y.W, MOVS.W 16-bit data Data
transfer
MOVS.L 32-bit data
A0G, A1G MOVS.W Data Data
transfer
MOVS.L Data
DSP Fixed-point, PDMSB,
PSHA
Sign* 32-bit data X0, X1
Y0, Y1
M0, M1
Integer Sign* 16-bit data
Logical, PSHL, PMULS 16-bit data
MOVS.W 16-bit data Data
transfer
MOVS.L 32-bit data
Note: * The data is sign-extended and input to the ALU.