Renesas SH7641 - Manual (Page 89)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 39 of 982
REJ09B0023-0400
31 32 39
A0 A0G
A1G A1
M0
M1
X0
X1
Y0
Y1
0 1 2 3 4 5 6 7
DC CS [2:0] V N Z GT
8 31
0
(a) DSP Data Registers
(b) DSP Status Register (DSR)
Reset status
DSR: All
zeros
Others: Undefined
Figure 2.7 DSP Registers
A0G
32 0 39
31 16
A0
A1
M0
M1
X0
X1
Y0
Y1
0 7
A1G
DSR
16 bits
16 bits
8 bits 32 bits
LDB
XDB
YDB
MOVX.W
MOVS.W,
MOVS.L MOVS.W,
MOVS.L
MOVY.W
Figure 2.8 Connections of DSP Registers and Buses