Quatech QSP-100 - Manual (Page 36)

7. Hardware Information
The QSP-100's four asynchronous serial ports are implemented using 4 standard 16C550
UARTs. Each of these UARTs requires 8 bytes of I/O space and when enabled
Base Address + 24 Channel D
Base Address + 16 Channel C
Base Address + 8 Channel B
Base Address + 0 Channel A
Address assignment QSP-100 RS-232 channel
which requires the QSP-100 to be located on an even 32-byte (20H) boundary (e.g. 300H, 320H,
340H, etc.).
Each 16C550 UART contains 8 I/O registers. The last of these registers, located at (Base address
+ 7), is referred to as the 'Scratchpad Register' and provides no functionality to the UART. In
place of this Scratchpad Register, the QSP-100 implements an interrupt status register which can
be accessed at (Base address + 7) of any UART. The purpose of the interrupt status register is to
give the software programmer an easy way to inspect the interrupt state of the entire QSP-100
with a single input operation. The format of the interrupt status register is shown below:
Intr A Intr B Intr C Intr D 0 0 0 0
D0 D1 D2 D3 D4 D5 D6 D7
When one or more UARTs have interrupts pending, the associated bit(s) in the interrupt status
register are set to logic 1. When all the pending interrupts have been serviced for a specific
UART, its interrupt status bit will be cleared to logic 0 automatically. When all the pending
interrupts from all UARTs have been serviced, the entire interrupt status register will return logic
0. The application program should not exit its interrupt service routine until all pending inter-
rupts from all channels have been serviced (interrupt status register = 0) or no additional inter-
rupts will be received.
If an application requires the UARTs' Scratchpad Registers, the interrupt status register can be
disabled using the "p" option on the QSP-100 Client Driver for DOS or the DOS Enabler
command lines.
QSP-100 Users Manual 33