Toshiba H1 Series - Manual (Page 232)

TMP92CZ26A
92CZ26A-229
(4) Read data shift function
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in
the next state. When this read data shift function is used, the read cycle requires additional
one state. The write cycle is not affected. The timing waveforms for various cases are shown
below.
(a) 1-word read, the read data shift function disabled (SDACR<SRCS> = “0”)
(b) 1-word read, the read data shift function enabled (SDACR<SRDS> = “1”,
<SRDSCK>=”0”)
CPU data read
SDCLK
COMMAND
ACTIVE NOP NOP READ NOP
D15-D0 DIN1
ACTIVE
A15-A0 Row Address ColumnAddress
Internal system
clock
Internal dat bus
DIN1
Row Address
READ
Column
Address
SDCLK
COMMAND ACTIVE NOP NOP READ NOP
D15-D0 DIN1
ACTIVE
A15-A0 Row Address
NOP
Internal system
clock
Internal data bus
DIN1
External data latch CPU data read
Row Address ColumnAddress