Toshiba H1 Series - Manual (Page 434)

TMP92CZ26A
92CZ26A-431
4. If ACK handshake from host is received,
• Set STATU to READY.
• Assert INT_STATUS interrupt.
It finishes normally by above transaction.
If it is time out without receiving ACK from host,
• Set STATUS register to TX_ERR and state return IDLE. And wait
restring status stage.
At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register.
(c-3-2) OUT status stage
Below is transaction format of OUT status stage.
• Token: OUT
• Data: DATA1 (0 data length)
• Handshake: ACK, NAK, STALL
Control flow
Below is transaction flow of OUT status stage in UDC.
1. Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.
2. STATUS register state is confirmed.
• INVALID condition: State return to IDLE.
• STALL condition: Data is cleared, stall handshake is returned,
and state return to IDLE.
It confirm whether EOP register is accessed or not by external. If it is
not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.
3. If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are received.
4. If there is not error in data, ACK handshake is transmitted to host.
• Set STATUS to READY.
• Assert INT_STATUS interrupt.
It finishes normally by above transaction.
If there is error in data, ACK handshake is not returned.
• Set RX_ERR to STATUS register and return to IDLE. It waits retrying
status stage.
At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register. Sequence of this protocol refers
to section supplement.