Tnetx4090 thunderswitch ii, Switch – Texas Instruments THUNDERSWITCH II TNETX4090 User Manual
Page 70
TNETX4090
ThunderSWITCH II
9-PORT 100-/1000-MBIT/S ETHERNET
SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
70
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
DIO and DMA reads (see Figure 26)
NO.
MIN
MAX
UNIT
1
tw(SCSL)
Pulse duration, SCS low
2tc
ns
2
tsu(SRNW)
Setup time, SRNW valid before SCS
↓
0
ns
3
tsu(SAD)
Setup time, SAD1–SAD0, SDMA valid before SCS
↓
0
ns
4
th(SRNW)
Hold time, SRNW low after SRDY
↓
0
ns
5
th(SAD)
Hold time, SAD1–SAD0, SDMA valid after SRDY
↓
0
ns
6
th(SCSL)
Hold time, SCS low after SRDY
↓
0
ns
7
tsu(SDATAD)
Setup time from SRDY
↓
to SDATA7–SDATA0 driven
0
ns
8
td(SRDYZH)
Delay time from SCS
↓
to SRDY
↑
10
ns
9
td(SRDYHL)
Delay time from SCS
↓
to SRDY
↓
0
†
ns
10
td(SDATAZ)
Delay time from SCS
↑
to SDATA7–SDATA0 3-state
0
10
ns
11
td(SRDYLH)
Delay time from SCS
↑
to SRDY
↑
tc
2tc+10
ns
12
th(SCSH)
Hold time, SCS high after SRDY
↑
0
ns
13
tw(SRDY)
Pulse duration, SRDY high
tc
ns
† When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08)
between SCS being asserted and SRDY being asserted.
ООООООООО
ООООООООО
ООО
ООО
ОООООООООО
ОООООООООО
ОООООООООО
ОООО
ОООО
ОООО
SCS
6
10
12
9
2
8
3
1
4
5
7
SRNW
SAD1–SAD0
SDMA
SDATA7–
SDATA0
SRDY
11
13
Figure 26. DIO and DMA Reads