Xilinx V2.1 - Manual (Page 121)

State Machine 121
Xilinx Blocks
The Registered Mealy State Machine block is configured with next state and output
matrices obtained from the next state/output table discussed above. These matrices
are constructed as follows:
Figure 3-86: Construction of Next State and Output matrices
The rows of the matrices correspond to the current state, and columns correspond to
the input value.
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-87: Registered Mealy State Machine block parameters dialog box
The next state logic, state register, output logic, and output register are implemented
using high speed dedicated block RAM. Of the four blocks in the state machine
library, this is the fastest and most area efficient. However, the output is registered
and thus the input does not affect the output instantaneously.