Xilinx V2.1 - Manual (Page 97)

MATLAB I/O 97
Xilinx Blocks
LogiCOREs, as well as signals and control circuits to drive the clock network.
Consequently, most System Generator blocks do not provide an explicit enable port.
There are two exceptions> the Register block and the Addressable Shift Register
block, which fundamentally require a CE port in order to target a high performance
hardware implementation.
Simulink Enabled Subsystems can be used to enable blocks and subsystems. In order to
support System Generator’s bit and cycle true modeling in Simulink, it is required
that the enable port on an enabled subsystem be driven by the Enable Adapter block,
found in the Xilinx blockset’s MATLAB I/O library. An example of this requirement is
shown in the figure below. This shows an address generation model for a MAC-based
FIR filter. The
DownCount subsystem is stalled for a single sample period when the
CoefCount counter value is equal to the number of filter taps (in this case, 96 taps).
Figure 3-67: Example of enabled subsystem
The following blocks cannot be placed in an enabled subsystem with System
Generator v2.1. The blocks are: CIC, Convolutional Encoder, FIR, FFT, Gateway In,
Gateway Out, RS Decoder, RS Encoder, and Viterbi Decoder.
Enable Adapter
When using an enabled subsystem that contains Xilinx blocks, the
enable port must be driven by a Xilinx Enable Adapter block. This
block is a required interface to any enabled subsystem that contains a
System Generator block. The Enable Adapter block’s output port must
drive the subsystem’s enable port.
Gateway In
The Xilinx Gateway In block is the input into the Xilinx FPGA part of
your Simulink design. It converts Simulink double precision input to
the System Generator fixed point type, and defines an input port for
the top level of the HDL design generated by System Generator.