Xilinx LogiCore PCI v3.0 - Manual (Page 11)

PCI v3.0.151 Getting Started Guide www.xilinx.com 11
UG157 August 31, 2005
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Chapter 1
Getting Started
The PCI interface provides a fully verified, pre-implemented PCI bus interface available in
both 32-bit and 64-bit versions with support for operation at 33 MHz and 66 MHz. This
guide defines the supported design flows for both the 32-bit and 64-bit interfaces targeting
devices based on the Virtex and Spartan architectures. In addition, an example design is
provided in both Verilog-HDL and VHDL that lets you simulate, synthesize, and
implement the interface to understand the PCI design flow.
About the Example Design
The example design is a simple user application provided as a training tool and design
flow test. The example design consists of the user application Ping, and supporting files for
simulation and implementation. The PCI32 interface ships with the ping32 design, and the
PCI64 interface ships with the ping64 design. The examples in this document reference
ping64. If you are using the 32-bit core, substitute ping32 for ping64.
The Ping design includes a testbench capable of generating simple read and write
transactions. This stimulation generation capability is used to set up the configuration
space of the design, and then perform some simple transactions. In addition, a special
configuration file is provided, and the testbench makes assumptions about the size and
number of base address registers used.
Users may change the core options related to implementation, that is, the options that
relate to the selected FPGA architecture. However, users must not change core options that
alter the functional behavior of the PCI core; such changes cause unpredictable results in
the simulation of the example design. For custom designs, users have the flexibility to
change the PCI core configuration as described in the PCI v3.0 User Guide.
Step-by-step instructions using supported design tools are provided to simulate,
synthesize, and implement the Ping example design.
Additional Documentation
For more information about the PCI interface core, see the following documents, located on
the
PCI product page :
•
PCI Release Notes
•
PCI User Guide
Further information is available in the Mindshare PCI System Architecture text, and the
PCI Local Bus Specification, available from the PCI Special Interest Group site.