Xilinx DS610 User Manual
Spartan-3a dsp fpga family data sheet, Module 1: introduction and ordering information, Module 2: functional description
DS610 October 4, 2010
Product Specification
1
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Module 1:
Introduction and Ordering Information
•
Introduction
•
Features
•
Architectural Overview
•
Configuration Overview
•
General I/O Capabilities
•
Supported Packages and Package Marking
•
Ordering Information
Module 2:
Functional Description
The functionality of the Spartan®-3A DSP FPGA family is
described in the following documents.
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: Spartan-3 Generation FPGA User Guide
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Clocking Resources
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Digital Clock Managers (DCMs)
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Block RAM
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Configurable Logic Blocks (CLBs)
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Distributed RAM
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SRL16 Shift Registers
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Carry and Arithmetic Logic
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I/O Resources
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Programmable Interconnect
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ISE® Software Design Tools and IP Cores
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Embedded Processing and Control Solutions
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Pin Types and Package Overview
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Package Drawings
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Powering FPGAs
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Power Management
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: Spartan-3 Generation Configuration User Guide
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Configuration Overview
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Configuration Pins and Behavior
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Bitstream Sizes
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Detailed Descriptions by Mode
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Master Serial Mode using Platform Flash PROM
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Master SPI Mode using Commodity Serial Flash
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Master BPI Mode using Commodity Parallel Flash
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Slave Parallel (SelectMAP) using a Processor
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Slave Serial using a Processor
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JTAG Mode
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ISE iMPACT Programming Examples
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MultiBoot Reconfiguration
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Design Authentication using Device DNA
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XtremeDSP™ DSP48A for Spartan-3A DSP
FPGAs User Guide
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DSP48A Slice Design Considerations
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DSP48A Architecture Highlights
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18 x 18-Bit Multipliers
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48-Bit Accumulator
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18-bit Pre-Adder
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DSP48A Application Examples
Module 3:
DC and Switching Characteristics
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DC Electrical Characteristics
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Absolute Maximum Ratings
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Supply Voltage Specifications
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Recommended Operating Conditions
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Switching Characteristics
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I/O Timing
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Configurable Logic Block (CLB) Timing
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Digital Clock Manager (DCM) Timing
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Block RAM Timing
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XtremeDSP Slice Timing
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Configuration and JTAG Timing
Module 4:
Pinout Descriptions
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Pin Descriptions
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Package Overview
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Pinout Tables
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Footprint Diagrams
1
Spartan-3A DSP FPGA Family Data Sheet
DS610 October 4, 2010
Product Specification
Document Outline
- Spartan-3A DSP FPGA Family Data Sheet
- Introduction and Ordering Information
- Functional Description
- DC and Switching Characteristics
- DC Electrical Characteristics
- Switching Characteristics
- Software Version Requirements
- I/O Timing
- Timing Measurement Methodology
- Using IBIS Models to Simulate Load Conditions in Application
- Simultaneously Switching Output Guidelines
- Configurable Logic Block (CLB) Timing
- Clock Buffer/Multiplexer Switching Characteristics
- Block RAM Timing
- DSP48A Timing
- Digital Clock Manager (DCM) Timing
- DNA Port Timing
- Suspend Mode Timing
- Configuration and JTAG Timing
- General Configuration Power-On/Reconfigure Timing
- Configuration Clock (CCLK) Characteristics
- Master Serial and Slave Serial Mode Timing
- Slave Parallel Mode Timing
- Serial Peripheral Interface (SPI) Configuration Timing
- Byte Peripheral Interface (BPI) Configuration Timing
- IEEE 1149.1/1532 JTAG Test Access Port Timing
- Revision History
- Pinout Descriptions