Input setup and hold times – Xilinx DS610 User Manual
Page 22
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
22
Input Setup and Hold Times
Table 19: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
DELAY_
VALUE
Device
Speed
Units
-5
-4
Min
Min
Setup Times
T
IOPICK
Time from the setup of data at the Input
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). No Input
Delay is programmed.
LVCMOS25
IFD_DELAY_VALUE=0
XC3SD1800A
1.65
1.81
ns
XC3SD3400A
1.51
1.88
ns
T
IOPICKD
Time from the setup of data at the Input
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). The
Input Delay is programmed.
LVCMOS25
1
XC3SD1800A
2.09
2.24
ns
2
2.67
2.83
ns
3
3.25
3.64
ns
4
3.75
4.20
ns
5
3.69
4.16
ns
6
4.47
5.09
ns
7
5.27
6.02
ns
8
5.79
6.63
ns
1
XC3SD3400A
2.07
2.44
ns
2
2.57
3.02
ns
3
3.44
3.81
ns
4
4.01
4.39
ns
5
3.89
4.26
ns
6
4.43
5.08
ns
7
5.20
5.95
ns
8
5.70
6.55
ns
Hold Times
T
IOICKP
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF) to
the point where data must be held at the
Input pin. No Input Delay is programmed.
LVCMOS25
0
XC3SD1800A
–0.63 –0.52
ns
XC3SD3400A
–0.56 –0.56
ns