Xilinx DS610 - Manual (Page 93)

Spartan-3A DSP FPGA Family: Pinout Descriptions
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 93
3 IO_L23N_3 K2 I/O
3 IO_L23P_3 K3 I/O
3 IO_L22N_3 K4 I/O
3 IO_L22P_3 K5 I/O
3 IO_L18P_3 K6 I/O
3 IO_L13P_3 K7 I/O
3 IO_L05N_3 K8 I/O
3 IO_L05P_3 K9 I/O
3 IP_L24P_3 J1 INPUT
3 IP_L20N_3/VREF_3 J2 VREF
3 IP_L20P_3 J3 INPUT
3 IO_L19N_3 J4 I/O
3 IO_L19P_3 J5 I/O
3 IO_L13N_3 J6 I/O
3 IO_L10P_3 J7 I/O
3 IO_L01P_3 J8 I/O
3 IO_L01N_3 J9 I/O
3 IO_L17N_3 H1 I/O
3 IO_L17P_3 H2 I/O
3 IP_3/VREF_3 H4 VREF
3 IO_L10N_3 H6 I/O
3 IO_L03N_3 H7 I/O
3 IP_3 G1 INPUT
3 IO_L14P_3 G3 I/O
3 IO_L09N_3 G4 I/O
3 IO_L03P_3 G6 I/O
3 IO_L11N_3 F2 I/O
3 IO_L14N_3 F3 I/O
3 IO_L07N_3 F4 I/O
3 IO_L09P_3 F5 I/O
3 IO_L11P_3 E1 I/O
3 IO_L07P_3 E3 I/O
3 IO_L06N_3 E4 I/O
3 IO_L06P_3 D3 I/O
3 IP_3/VREF_3 C1 VREF
3 IO_L02N_3 B1 I/O
3 IO_L02P_3 B2 I/O
3 IP_L66P_3 AE1 INPUT
3 IP_L66N_3/VREF_3 AE2 VREF
Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA (Cont’d)
Bank XC3SD3400A Pin Name
FG676
Ball
Type
3 IO_L65P_3 AD1 I/O
3 IO_L65N_3 AD2 I/O
3 IO_L60N_3 AC1 I/O
3 IO_L64P_3 AC2 I/O
3 IO_L64N_3 AC3 I/O
3 IO_L60P_3 AB1 I/O
3 IO_L55P_3 AA2 I/O
3 IO_L55N_3 AA3 I/O
3 IP_3/VREF_3 AA5 VREF
3 VCCO_3 W5 VCCO
3 VCCO_3 T2 VCCO
3 VCCO_3 T8 VCCO
3 VCCO_3 P5 VCCO
3 VCCO_3 L2 VCCO
3 VCCO_3 L8 VCCO
3 VCCO_3 H5 VCCO
3 VCCO_3 E2 VCCO
3 VCCO_3 C2 VCCO
3 VCCO_3 AB2 VCCO
GND GND W8 GND
GND GND W14 GND
GND GND W19 GND
GND GND W24 GND
GND GND W25 GND
GND GND V3 GND
GND GND U10 GND
GND GND U13 GND
GND GND U17 GND
GND GND U25 GND
GND GND T1 GND
GND GND T6 GND
GND GND T12 GND
GND GND T14 GND
GND GND T16 GND
GND GND T21 GND
GND GND T26 GND
GND GND R11 GND
GND GND R13 GND
GND GND R15 GND
Table 68: Spartan-3A DSP FG676 Pinout for
XC3SD3400A FPGA (Cont’d)
Bank XC3SD3400A Pin Name
FG676
Ball
Type