Xilinx DS610 - Manual (Page 27)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 27
Output Propagation Times
Table 23: Timing for the IOB Output Path
Symbol Description Conditions Device
Speed Grade
Units -5 -4
Max Max
Clock-to-Output Times
T
IOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin LVCMOS25 (2) , 12 mA output
drive, Fast slew rate
All 2.87 3.13 ns
Propagation Times
T
IOOP
The time it takes for data to travel from
the IOB’s O input to the Output pin LVCMOS25 (2) , 12 mA output
drive, Fast slew rate
All 2.78 2.91 ns
Set/Reset Times
T
IOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin LVCMOS25 (2) , 12 mA output
drive, Fast slew rate
All 3.63 3.89 ns
T
IOGSRQ
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin 8.62 9.65 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10 .
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from
Table 25 .