User i/os by bank – Xilinx DS610 User Manual
Page 84
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Spartan-3A DSP FPGA Family: Pinout Descriptions
DS610 (v3.0) October 4, 2010
Product Specification
84
User I/Os by Bank
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package
Package
Edge
I/O Bank
Maximum I/Os
and
Input-Only
All Possible I/O Pins by Type
I/O
INPUT
DUAL
CLK
Top
0
128
82
28
1
9
8
Right
1
130
67
15
30
10
8
Bottom
2
129
68
21
21
11
8
Left
3
132
97
18
0
9
8
TOTAL
519
314
82
52
39
32
Notes:
1.
28 VREF are on INPUT pins.
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