Xilinx DS610 - Manual (Page 52)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 52
Configuration Clock (CCLK) Characteristics
Table 46: Master Mode CCLK Output Period by ConfigRate Option Setting
Symbol Description
ConfigRate
Setting (1)
Temperature
Range
Minimum Maximum Units
T
CCLK1
CCLK clock period by
ConfigRate setting
1
(power-on value)
Commercial 1,254
2,500
ns
Industrial 1,180 ns
T
CCLK3
3
Commercial 413
833
ns
Industrial 390 ns
T
CCLK6
6
(default)
Commercial 207
417
ns
Industrial 195 ns
T
CCLK7
7
Commercial 178
357
ns
Industrial 168 ns
T
CCLK8
8
Commercial 156
313
ns
Industrial 147 ns
T
CCLK10
10
Commercial 123
250
ns
Industrial 116 ns
T
CCLK12
12
Commercial 103
208
ns
Industrial 97 ns
T
CCLK13
13
Commercial 93
192
ns
Industrial 88 ns
T
CCLK17
17
Commercial 72
147
ns
Industrial 68 ns
T
CCLK22
22
Commercial 54
114
ns
Industrial 51 ns
T
CCLK25
25
Commercial 47
100
ns
Industrial 45 ns
T
CCLK27
27
Commercial 44
93
ns
Industrial 42 ns
T
CCLK33
33
Commercial 36
76
ns
Industrial 34 ns
T
CCLK44
44
Commercial 26
57
ns
Industrial 25 ns
T
CCLK50
50
Commercial 22
50
ns
Industrial 21 ns
T
CCLK100
100
Commercial 11.2
25
ns
Industrial 10.6 ns
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.