Xilinx DS610 - Manual (Page 28)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 28
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
Symbol Description Conditions Device
Speed Grade
Units -5 -4
Max Max
Synchronous Output Enable/Disable Times
T
IOCKHZ
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state LVCMOS25, 12 mA
output drive, Fast slew
rate All 1.13 1.39 ns
T
IOCKON
(2) Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data All 3.08 3.35 ns
Asynchronous Output Enable/Disable Times
T
GTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state LVCMOS25, 12 mA
output drive, Fast slew
rate All 9.47 10.36 ns
Set/Reset Times
T
IOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state LVCMOS25, 12 mA
output drive, Fast slew
rate All 1.61 1.86 ns
T
IOSRON
(2) Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data All 3.57 3.82 ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10 .
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
Table 25 .