Xilinx DS610 - Manual (Page 58)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 58
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 14
Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol Description Minimum Maximum Units
T
CCLK1
Initial CCLK clock period See Table 46
T
CCLKn
CCLK clock period after FPGA loads ConfigRate setting See Table 46
T
MINIT
Setup time on M[2:0] mode pins before the rising edge of INIT_B 50 – ns
T
INITM
Hold time on M[2:0] mode pins after the rising edge of INIT_B 0 – ns
T
INITADDR
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid 5 5 T
CCLK1
cycles
T
CCO
Address A[25:0] outputs valid after CCLK falling edge See Table 50
T
DCC
Setup time on D[7:0] data inputs before CCLK rising edge See T
SMDCC
in Table 51
T
CCD
Hold time on D[7:0] data inputs after CCLK rising edge 0 – ns
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Data Data Data
Address Address
Data
Address
Byte 0
000_0000
INIT_B
<0:1:0>
M[2:0]
T
MINIT
T
INITM
LDC[2:0]
HDC
CSO_B
Byte 1
000_0001
CCLK
A[25:0]
D[7:0]
T
DCC
T
CCD
T
AVQV
T
CCLK1
(Input)
T
INITADDR
T
CCLKn
T
CCLK1
T
CCO
PUDC_B
New ConfigRate active
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
(Input)
PROG_B
(Input)
DS529-3_05_090610
(Open-Drain)
Shaded values indicate specifications on attached parallel NOR Flash PROM.