Xilinx DS610 - Manual (Page 61)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 61
Revision History
The following table shows the revision history for this document.
Date Version Revision
04/02/07 1.0 Initial Xilinx release.
05/25/07 1.0.1 Minor edits.
06/18/07 1.2 Updated for v1.29 production speed files. Noted banking rules in Table 11 and Table 12 . Added
DIFF_HSTL_I and DIFF_HSTL_III to Table 12 , Table 13 , and Table 26 . Updated TMDS DC characteristics
in Table 13 . Updated I/O Test Method values in Table 26 . Added Simultaneously Switching Output limits in
Table 28 . Updated DSP48A timing symbols, descriptions, and values in Table 34 . Added power-on timing in
Table 45 . Added CCLK specifications for Commercial in Table 46 through Table 48 . Updated Slave Parallel
timing in Table 51 . Updated JTAG specifications in Table 56 .
07/16/07 2.0 Added Low-power options and updated typical values for quiescent current in Table 9 . Updated DSP48A
timing in Table 34 and Table 35 .
06/02/08 2.1 Improved V
CCAUXT
and V
CCO2T
POR minimum in Table 4 and updated V
CCO
POR levels in Figure 10 . Added
V
IN
to Recommended Operating Conditions in Table 7 and added reference to XAPP459 , “Eliminating I/O
Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical
I
CCINTQ
and I
CCAUXQ
quiescent current values by 20%-44% in Table 9 . Increased V
IL
max to 0.4V for
LVCMOS12/15/18 and improved V
IH
min to 0.7V for LVCMOS12 in Table 10 . Changed V
OL
max to 0.4V and
V
OH
min to V
CCO
–0.4V for LVCMOS15/18 in Table 11 . Added reference to V
CCAUX
in Simultaneously
Switching Output Guidelines . Removed DNA_RETENTION limit of 10 years in Table 14 since number of
Read cycles is the only unique limit. Updated speed files to v1.31 in Table 16 and elsewhere. Updated IOB
Setup and Hold times with device-specific values in Table 19 . Added reference to Sample Window in
Table 20 . Updated IOB Propagation times with device-specific values in Table 21 . Improved SSTL_18_II
SSO value in Table 28 . Improved F
BUFG
for -4 to 334 MHz in Table 32 . Added references to 375 MHz
performance via SCD 4103 in Table 32 , Table 37 , Table 38 , and Table 39 . Added explanatory footnotes to
DSP48A Timing tables. Simplified DSP48A F
MAX
to value with all registers used in Table 35 . Improved
FBUFG in Table 32 for -4 speed grade. Updated CCLK output maximum period in Table 46 to match
minimum frequency in Table 47. Replaced BPI with SPI specification descriptions in Table 52 . Corrected BPI
Figure 14 and Table 54 from falling edge to rising edge. Added references to Spartan-3 Generation User
Guides. Updated links.
03/11/09 2.2 Changed typical quiescent current temperature from ambient to quiescent. Updated selected I/O standard
DC characteristics. Removed PCIX IOSTANDARD due to limited PCIX interface support. Added T
IOPI
and
T
IOPID
to Table 21 . Updated BPI configuration waveforms in Figure 14 and updated Table 55 . Removed
references to SCD 4103.
10/04/10 3.0 Added I
IK
to Table 3 . Updated description for V
IN
in Table 7 including adding note 4. Also, added note 2 to I
L
in Table 8 to note potential leakage between pins of a differential pair. Added note 6 to Table 10 . Updated
notes 5 and 6 in Table 12 . Corrected symbols for T
SUSPEND_GTS
and T
SUSPEND_GWE
in Table 44 .