Xilinx DS610 - Manual (Page 43)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 43
Table 35: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A
Symbol Description Pre-adder Multiplier Post-adder
Speed Grade
Units -5 -4
Max Max
Clock to Out from Output Register Clock to Output Pin
T
DSPCKO_PP
CLK (PREG) to P output – – – 1.26 1.44 ns
Clock to Out from Pipeline Register Clock to Output Pins
T
DSPCKO_PM
CLK (MREG) to P output – Yes Yes 3.16 3.63 ns
– Yes No 1.94 2.23 ns
Clock to Out from Input Register Clock to Output Pins
T
DSPCKO_PA
CLK (AREG) to P output – Yes Yes 6.33 7.27 ns
T
DSPCKO_PB
CLK (BREG) to P output Yes Yes Yes 7.45 8.56 ns
T
DSPCKO_PC
CLK (CREG) to P output – – Yes 3.37 3.87 ns
T
DSPCKO_PD
CLK (DREG) to P output Yes Yes Yes 7.33 8.42 ns
Combinatorial Delays from Input Pins to Output Pins
T
DSPDO_AP
T
DSPDO_BP
A or B input to P output – No Yes 2.78 3.19 ns
– Yes No 4.60 5.28 ns
– Yes Yes 5.65 6.49 ns
T
DSPDO_BP
B input to P output Yes No No 3.49 4.01 ns
Yes Yes No 5.79 6.65 ns
Yes Yes Yes 6.74 7.74 ns
T
DSPDO_CP
C input to P output – – Yes 2.76 3.17 ns
T
DSPDO_DP
D input to P output Yes Yes Yes 6.81 7.82 ns
T
DSPDO_OPP
OPMODE input to P output Yes Yes Yes 7.12 8.18 ns
Maximum Frequency
F
MAX
All registers used Yes Yes Yes 287 250 MHz
Notes:
1. To reference the DSP48A block diagram, see UG431 : XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.
2. "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not
applicable.
3. The numbers in this table are based on the operating conditions set forth in Table 7 .