Xilinx DS610 - Manual (Page 40)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 40
Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Symbol Description Minimum
Maximum
Units Speed Grade
-5 -4
T
GIO
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
– 0.22 0.23 ns
T
GSI
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
– 0.56 0.63 ns
F
BUFG
Frequency of signals distributed on global buffers (all sides) 0 350 334 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7 .