Xilinx DS610 - Manual (Page 15)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 15
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
I
OL
(mA)
I
OH
(mA)
V
OL
Max (V)
V
OH
Min (V)
LVTTL (3) 2 2 –2 0.4 2.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
16 16 –16
24 24 –24
LVCMOS33 (3) 2 2 –2 0.4 V
CCO
– 0.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
16 16 –16
24 (5) 24 –24
LVCMOS25 (3) 2 2 –2 0.4 V
CCO
– 0.4
4 4 –4
6 6 –6
8 8 –8
12 12 –12
16 (5) 16 –16
24 (5) 24 –24
LVCMOS18 (3) 2 2 –2 0.4 V
CCO
– 0.4
4 4 –4
6 6 –6
8 8 –8
12 (5) 12 –12
16 (5) 16 –16
LVCMOS15 (3) 2 2 –2 0.4 V
CCO
– 0.4
4 4 –4
6 6 –6
8 (5) 8 –8
12 (5) 12 –12
LVCMOS12 (3) 2 2 –2 0.4 V
CCO
– 0.4
4 (5) 4 –4
6 (5) 6 –6
PCI33_3 (4) 1.5 –0.5 10% V
CCO
90% V
CCO
PCI66_3 (4) 1.5 –0.5 10% V
CCO
90% V
CCO
HSTL_I (5) 8 –8 0.4 V
CCO
– 0.4
HSTL_III (5) 24 –8 0.4 V
CCO
– 0.4
HSTL_I_18 8 –8 0.4 V
CCO
– 0.4
HSTL_II_18 (5) 16 –16 0.4 V
CCO
– 0.4
HSTL_III_18 24 –8 0.4 V
CCO
– 0.4
SSTL18_I 6.7 –6.7 V
TT
– 0.475 V
TT
+ 0.475
SSTL18_II (5) 13.4 –13.4 V
TT
– 0.603 V
TT
+ 0.603
SSTL2_I 8.1 –8.1 V
TT
– 0.61 V
TT
+ 0.61
SSTL2_II (5) 16.2 –16.2 V
TT
– 0.81 V
TT
+ 0.81
SSTL3_I 8 –8 V
TT
– 0.6 V
TT
+ 0.6
SSTL3_II (5) 16 –16 V
TT
– 0.8 V
TT
+ 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 7 and Table 10 .
2. Descriptions of the symbols used in this table are as follows:
I
OL
—the output current condition under which VOL is tested
I
OH
—the output current condition under which VOH is tested
V
OL
— the output voltage that indicates a Low logic level
V
OH
—the output voltage that indicates a High logic level
V
CCO
—the supply voltage for output drivers
V
TT
—the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same V
OL
and V
OH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see
www.xilinx.com/products/
design_resources/conn_central/protocols/pci_pcix.htm . The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
5. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the Using I/O
Resources chapter in
UG331 .
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
IOSTANDARD
Attribute
Test
Conditions
Logic Level
Characteristics
I
OL
(mA)
I
OH
(mA)
V
OL
Max (V)
V
OH
Min (V)