Spartan-3a dsp fpga family: pinout descriptions, Bank 0 ba n k 1, Bank 2 – Xilinx DS610 User Manual

Page 86

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Spartan-3A DSP FPGA Family: Pinout Descriptions

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

86

Right Half of FG676
Package (Top View)

Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Right Half)

14

15

16

17

18

19

20

21

22

23

24

25

26

I/O

L26N_0

GCLK7

I/O

L23N_0

GND

INPUT

I/O

L18N_0

I/O

L15N_0

I/O

L14N_0

GND

I/O

L07N_0

INPUT

∇

INPUT

∇

TCK

GND

A

I/O

L26P_0

GCLK6

I/O

L23P_0

VCCO_0

I/O

L19N_0

I/O

L18P_0

I/O

L15P_0

I/O

L14P_0

VREF_0

I/O

L09N_0

VCCO_0

I/O

L07P_0

INPUT

∇

INPUT

L65N_1

∇

INPUT

L65P_1

VREF_1

∇

B

GND

I/O

L22N_0

I/O

L21N_0

I/O

L19P_0

I/O

L17N_0

GND

I/O

L11N_0

I/O

L09P_0

I/O

L05N_0

I/O

L06N_0

GND

I/O

L63N_1

A23

I/O

L63P_1

A22

C

INPUT

VREF_0

INPUT

∇

I/O

L22P_0

I/O

L21P_0

I/O

L17P_0

INPUT

∇

I/O

L11P_0

I/O

L10N_0

I/O

L05P_0

I/O

L06P_0

I/O

L61N_1

I/O

L61P_1

I/O

L60N_1

D

I/O

L24P_0

I/O

L20N_0

VREF_0

VCCAUX

I/O

L13N_0

INPUT

VCCO_0

INPUT

∇

I/O

L10P_0

VCCAUX

TDO

I/O

L56P_1

VCCO_1

I/O

L60P_1

E

I/O

L24N_0

I/O

L20P_0

GND

I/O

L13P_0

INPUT

∇

I/O

L02N_0

I/O

L01N_0

GND

I/O

L58P_1

VREF_1

I/O

L56N_1

I/O

L54N_1

I/O

L54P_1

GND

F

INPUT

I/O

L16P_0

INPUT

∇

I/O

L08N_0

INPUT

∇

I/O

L02P_0

VREF_0

I/O

L01P_0

I/O

L64N_1

A25

I/O

L58N_1

I/O

L51P_1

I/O

L51N_1

INPUT

L52N_1

VREF_1

∇

INPUT

L52P_1

∇

G

GND

I/O

L16N_0

VCCO_0

I/O

L08P_0

INPUT

GND

I/O

L64P_1

A24

I/O

L62N_1

A21

VCCO_1

INPUT

L48P_1

∇

INPUT

L48N_1

∇

INPUT

L44N_1

∇

INPUT

L44P_1

VREF_1

∇

H

I/O

L25N_0

GCLK5

INPUT

I/O

L12P_0

INPUT

VREF_0

VCCAUX

I/O

L59P_1

I/O

L59N_1

I/O

L62P_1

A20

I/O

L49N_1

I/O

L49P_1

GND

I/O

L43N_1

A19

I/O

L43P_1

A18

J

I/O

L25P_0

GCLK4

VCCINT

I/O

L12N_0

GND

I/O

L57N_1

I/O

L57P_1

I/O

L53N_1

I/O

L50N_1

I/O

L46N_1

I/O

L46P_1

INPUT

L40P_1

I/O

L41P_1

I/O

L41N_1

K

VCCINT

GND

VCCINT

I/O

L55N_1

I/O

L55P_1

VCCO_1

I/O

L53P_1

GND

I/O

L50P_1

INPUT

L40N_1

I/O

L38P_1

A12

VCCO_1

GND

L

GND

VCCINT

GND

VCCINT

I/O

L47N_1

I/O

L47P_1

I/O

L42N_1

A17

I/O

L45P_1

I/O

L45N_1

I/O

L38N_1

A13

INPUT

L36P_1

VREF_1

I/O

L35N_1

A11

I/O

L35P_1

A10

M

VCCINT

GND

VCCINT

I/O

L39N_1

A15

I/O

L39P_1

A14

I/O

L34N_1

RHCLK7

I/O

L42P_1

A16

I/O

L37N_1

VCCO_1

INPUT

L36N_1

I/O

L33N_1

RHCLK5

INPUT

L32N_1

INPUT

L32P_1

N

VCCINT VCCINT

GND

VCCAUX

I/O

L34P_1

IRDY1

RHCLK6

GND

I/O

L30N_1

RHCLK1

I/O

L30P_1

RHCLK0

I/O

L37P_1

I/O

L33P_1

RHCLK4

GND

I/O

L31N_1

TRDY1

RHCLK3

I/O

L31P_1

RHCLK2

P

VCCINT

GND

VCCINT

I/O

L27N_1

A7

I/O

L27P_1

A6

I/O

L22P_1

I/O

L22N_1

I/O

L25P_1

A2

I/O

L25N_1

A3

INPUT

L28P_1

VREF_1

INPUT

L28N_1

I/O

L29P_1

A8

I/O

L29N_1

A9

R

GND

VCCINT

GND

I/O

L17N_1

I/O

L17P_1

VCCO_1

I/O

L14N_1

GND

VCCAUX

I/O

L26P_1

A4

I/O

L26N_1

A5

VCCO_1

GND

T

VCCAUX

I/O

L35N_2

I/O

L42N_2

GND

I/O

L12N_1

I/O

L12P_1

I/O

L10N_1

I/O

L14P_1

I/O

L21N_1

I/O

L23P_1

I/O

L23N_1

VREF_1

INPUT

L24P_1

∇

INPUT

L24N_1

VREF_1

∇

U

Bank 0

Ba

n

k

1

I/O

L31P_2

I/O

L35P_2

I/O

L42P_2

I/O

L46N_2

I/O

L08P_1

I/O

L08N_1

SUSPEND

I/O

L10P_1

I/O

L18N_1

I/O

L21P_1

I/O

L19P_1

I/O

L19N_1

INPUT

L20N_1

VREF_1

∇

V

GND

I/O

L31N_2

VCCO_2

I/O

L46P_2

INPUT

∇

GND

I/O

L04P_1

I/O

L04N_1

VCCO_1

I/O

L18P_1

GND

INPUT

L16P_1

∇

INPUT

L20P_1

∇

W

I/O

L27P_2

GCLK0

I/O

L34N_2

D3

INPUT

VREF_2

I/O

L43N_2

INPUT

∇

INPUT

VREF_2

∇

I/O

L01P_1

HDC

I/O

L01N_1

LDC2

I/O

L13P_1

I/O

L13N_1

I/O

L15P_1

I/O

L15N_1

INPUT

L16N_1

∇

Y

I/O

L27N_2

GCLK1

I/O

L34P_2

INIT_B

GND

I/O

L43P_2

I/O

L47N_2

INPUT

∇

INPUT

VREF_2

GND

I/O

L09P_1

I/O

L09N_1

I/O

L11P_1

I/O

L11N_1

GND

A
A

VCCO_2

I/O

L30N_2

MOSI

CSI_B

I/O

L38N_2

INPUT

∇

I/O

L47P_2

VCCO_2

INPUT

∇

DONE

VCCAUX

I/O

L07P_1

I/O

L07N_1

VREF_1

VCCO_1

I/O

L06N_1

A
B

I/O

L29N_2

I/O

L30P_2

I/O

L38P_2

INPUT

INPUT

∇

I/O

L40N_2

I/O

L41N_2

I/O

L45N_2

I/O

2

I/O

L03P_1

A0

I/O

L03N_1

A1

I/O

L05N_1

I/O

L06P_1

A
C

I/O

L29P_2

I/O

L32P_2

AWAKE

INPUT

I/O

L33N_2

GND

I/O

L40P_2

I/O

L41P_2

I/O

L44N_2

I/O

L45P_2

INPUT

∇

GND

I/O

L02N_1

LDC0

I/O

L05P_1

A
D

I/O

L28N_2

GCLK3

I/O

L32N_2

DOUT

VCCO_2

I/O

L33P_2

I/O

L36N_2

D1

I/O

L37N_2

I/O

L39N_2

I/O

L44P_2

VCCO_2

I/O

L48N_2

I/O

L52N_2

CCLK

I/O

L51N_2

I/O

L02P_1

LDC1

A
E

I/O

L28P_2

GCLK2

INPUT

VREF_2

GND

INPUT

VREF_2

I/O

L36P_2

D2

I/O

L37P_2

I/O

L39P_2

GND

INPUT

VREF_2

I/O

L48P_2

I/O

L52P_2

D0

DIN/MISO

I/O

L51P_2

GND

A

F

Bank 2

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