Xilinx DS610 User Manual

Page 31

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Spartan-3A DSP FPGA Family: DC and Switching Characteristics

DS610 (v3.0) October 4, 2010

www.xilinx.com

Product Specification

31

LVCMOS12

Slow

2 mA

7.14

7.14

ns

4 mA

4.87

4.87

ns

6 mA

5.67

5.67

ns

Fast

2 mA

6.77

6.77

ns

4 mA

5.02

5.02

ns

6 mA

4.09

4.09

ns

QuietIO

2 mA

50.76

50.76

ns

4 mA

43.17

43.17

ns

6 mA

37.31

37.31

ns

PCI33_3

0.34

0.34

ns

PCI66_3

0.34

0.34

ns

HSTL_I

0.78

0.78

ns

HSTL_III

1.16

1.16

ns

HSTL_I_18

0.35

0.35

ns

HSTL_II_18

0.30

0.30

ns

HSTL_III_18

0.47

0.47

ns

SSTL18_I

0.40

0.40

ns

SSTL18_II

0.30

0.30

ns

SSTL2_I

0.00

0.00

ns

SSTL2_II

–0.05

–0.05

ns

SSTL3_I

0.00

0.00

ns

SSTL3_II

0.17

0.17

ns

Table 25:

Output Timing Adjustments for IOB

(Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

Add the

Adjustment

Below

Units

Speed Grade

-5

-4

Differential Standards

LVDS_25

1.16

1.16

ns

LVDS_33

0.46

0.46

ns

BLVDS_25

0.11

0.11

ns

MINI_LVDS_25

0.75

0.75

ns

MINI_LVDS_33

0.40

0.40

ns

LVPECL_25

Inputs Only

LVPECL_33

RSDS_25

1.42

1.42

ns

RSDS_33

0.58

0.58

ns

TMDS_33

0.46

0.46

ns

PPDS_25

1.07

1.07

ns

PPDS_33

0.63

0.63

ns

DIFF_HSTL_I_18

0.43

0.43

ns

DIFF_HSTL_II_18

0.41

0.41

ns

DIFF_HSTL_III_18

0.36

0.36

ns

DIFF_HSTL_I

1.01

1.01

ns

DIFF_HSTL_III

0.54

0.54

ns

DIFF_SSTL18_I

0.49

0.49

ns

DIFF_SSTL18_II

0.41

0.41

ns

DIFF_SSTL2_I

0.82

0.82

ns

DIFF_SSTL2_II

0.09

0.09

ns

DIFF_SSTL3_I

1.16

1.16

ns

DIFF_SSTL3_II

0.28

0.28

ns

Notes:

1.

The numbers in this table are tested using the methodology
presented in

Table 26

and are based on the operating conditions

set forth in

Table 7

,

Table 10

, and

Table 12

.

2.

These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.

3.

Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.

Table 25:

Output Timing Adjustments for IOB

(Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

Add the

Adjustment

Below

Units

Speed Grade

-5

-4

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