Xilinx DS610 - Manual (Page 41)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 41
Block RAM Timing
Table 33: Block RAM Timing
Symbol Description
Speed Grade
Units -5 -4
Min Max Min Max
Clock-to-Output Times
T
RCKO_DOA_NC
When reading from block RAM, the delay from the active transition at
the CLK input to data appearing at the DOUT output – 2.38 – 2.80 ns
T
RCKO_DOA
Clock CLK to DOUT output (with output register) – 1.24 – 1.45 ns
Setup Times
T
RCCK_ADDR
Setup time for the ADDR inputs before the active transition at the CLK
input of the block RAM 0.40 – 0.46 – ns
T
RDCK_DIB
Setup time for data at the DIN inputs before the active transition at the
CLK input of the block RAM 0.29 – 0.33 – ns
T
RCCK_ENB
Setup time for the EN input before the active transition at the CLK input
of the block RAM 0.51 – 0.60 – ns
T
RCCK_WEB
Setup time for the WE input before the active transition at the CLK input
of the block RAM 0.64 – 0.75 – ns
T
RCCK_REGCE
Setup time for the CE input before the active transition at the CLK input
of the block RAM 0.34 – 0.40 – ns
T
RCCK_RST
Setup time for the RST input before the active transition at the CLK
input of the block RAM 0.22 – 0.25 – ns
Hold Times
T
RCKC_ADDR
Hold time on the ADDR inputs after the active transition at the CLK
input 0.09 – 0.10 – ns
T
RCKC_DIB
Hold time on the DIN inputs after the active transition at the CLK input 0.09 – 0.10 – ns
T
RCKC_ENB
Hold time on the EN input after the active transition at the CLK input 0.09 – 0.10 – ns
T
RCKC_WEB
Hold time on the WE input after the active transition at the CLK input 0.09 – 0.10 – ns
T
RCKC_REGCE
Hold time on the CE input after the active transition at the CLK input 0.09 – 0.10 – ns
T
RCKC_RST
Hold time on the RST input after the active transition at the CLK input 0.09 – 0.10 – ns
Clock Timing
T
BPWH
High pulse width of the CLK signal 1.56 – 1.79 – ns
T
BPWL
Low pulse width of the CLK signal 1.56 – 1.79 – ns
Clock Frequency
F
BRAM
Block RAM clock frequency 0 320 0 280 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 7 .