Configuration, I/o capabilities – Xilinx DS610 User Manual
Page 4
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
Product Specification
4
Configuration
Spartan-3A DSP FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
•
Master Serial
•
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
•
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
•
Slave Serial, typically downloaded from a processor
•
Slave Parallel, typically downloaded from a processor
•
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Furthermore, Spartan-3A DSP FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A DSP FPGA contains a
unique, factory-programmed Device DNA identifier useful
for tracking purposes, anti-cloning designs, or IP protection.
I/O Capabilities
The Spartan-3A DSP FPGA SelectIO interface supports
many popular single-ended and differential standards.
shows the number of user I/Os as well as the
number of differential I/O pairs available for each
device/package combination. Some of the user I/Os are
unidirectional input-only pins as indicated in
Spartan-3A DSP FPGAs support the following single-ended
standards:
•
3.3V low-voltage TTL (LVTTL)
•
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
•
3.3V PCI at 33 MHz or 66 MHz
•
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
•
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
•
Spartan-3A DSP FPGAs support the following
differential standards:
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
•
Bus LVDS I/O at 2.5V
•
TMDS I/O at 3.3V
•
Differential HSTL and SSTL I/O
•
LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Device
CS484
CSG484
FG676
FGG676
User
Diff
User
Diff
XC3SD1800A
309
(60)
140
(78)
519
(110)
227
(131)
XC3SD3400A
309
(60)
140
(78)
469
(60)
213
(117)
Notes:
1.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of
input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O
banks that are restricted to differential inputs.