Xilinx DS610 User Manual
Page 33
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
33
The capacitive load (C
L
) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a C
L
value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
Differential
LVDS_25
–
V
ICM
– 0.125
V
ICM
+ 0.125
50
1.2
V
ICM
LVDS_33
–
V
ICM
– 0.125
V
ICM
+ 0.125
50
1.2
V
ICM
BLVDS_25
–
V
ICM
– 0.125
V
ICM
+ 0.125
1M
0
V
ICM
MINI_LVDS_25
–
V
ICM
– 0.125
V
ICM
+ 0.125
50
1.2
V
ICM
MINI_LVDS_33
–
V
ICM
– 0.125
V
ICM
+ 0.125
50
1.2
V
ICM
LVPECL_25
–
V
ICM
– 0.3
V
ICM
+ 0.3
N/A
N/A
V
ICM
LVPECL_33
–
V
ICM
– 0.3
V
ICM
+ 0.3
N/A
N/A
V
ICM
RSDS_25
–
V
ICM
– 0.1
V
ICM
+ 0.1
50
1.2
V
ICM
RSDS_33
–
V
ICM
– 0.1
V
ICM
+ 0.1
50
1.2
V
ICM
TMDS_33
–
V
ICM
– 0.1
V
ICM
+ 0.1
50
3.3
V
ICM
PPDS_25
–
V
ICM
– 0.1
V
ICM
+ 0.1
50
0.8
V
ICM
PPDS_33
–
V
ICM
– 0.1
V
ICM
+ 0.1
50
0.8
V
ICM
DIFF_HSTL_I_18
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_HSTL_II_18
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_HSTL_III_18
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
1.8
V
ICM
DIFF_HSTL_I
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_HSTL_III
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_SSTL18_I
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_SSTL18_II
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
0.9
V
ICM
DIFF_SSTL2_I
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
1.25
V
ICM
DIFF_SSTL2_II
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
1.25
V
ICM
DIFF_SSTL3_I
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
1.5
V
ICM
DIFF_SSTL3_II
–
V
ICM
– 0.5
V
ICM
+ 0.5
50
1.5
V
ICM
Notes:
1.
Descriptions of the relevant symbols are:
V
REF
– The reference voltage for setting the input switching threshold
V
ICM
– The common mode input voltage
V
M
– Voltage of measurement point on signal transition
V
L
– Low-level test voltage at Input pin
V
H
– High-level test voltage at Input pin
R
T
– Effective termination resistance, which takes on a value of 1 M
Ω when no parallel termination is required
V
T
– Termination voltage
2.
The load capacitance (C
L
) at the Output pin is 0 pF for all signal standards.
3.
According to the PCI specification. For information on PCI IP solutions, se
. The PCIX IOSTANDARD is available and
has equivalent characteristics but no PCI-X IP is supported.
Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Inputs
Outputs
(2)
Inputs and
Outputs
V
REF
(V)
V
L
(V)
V
H
(V)
R
T
(
Ω)
V
T
(V)
V
M
(V)