Xilinx DS610 - Manual (Page 10)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010 www.xilinx.com
Product Specification 10
Power Supply Specifications
Table 4: Supply Voltage Thresholds for Power-On Reset
Symbol Description Min Max Units
V
CCINTT
Threshold for the V
CCINT
supply 0.4 1.0 V
V
CCAUXT
Threshold for the V
CCAUX
supply 1.0 2.0 V
V
CCO2T
Threshold for the V
CCO
Bank 2 supply 1.0 2.0 V
Notes:
1. V
CCINT
, V
CCAUX
, and V
CCO
supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply V
CCINT
last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
2. To ensure successful power-on, V
CCINT
, V
CCO
Bank 2, and V
CCAUX
supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 5: Supply Voltage Ramp Rate
Symbol Description Min Max Units
V
CCINTR
Ramp rate from GND to valid V
CCINT
supply level 0.2 100 ms
V
CCAUXR
Ramp rate from GND to valid V
CCAUX
supply level 0.2 100 ms
V
CCO2R
Ramp rate from GND to valid V
CCO
Bank 2 supply level 0.2 100 ms
Notes:
1. V
CCINT
, V
CCAUX
, and V
CCO
supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply V
CCINT
last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
2. To ensure successful power-on, V
CCINT
, V
CCO
Bank 2, and V
CCAUX
supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol Description Min Units
V
DRINT
V
CCINT
level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V
V
DRAUX
V
CCAUX
level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V