Xilinx DS610 User Manual
Spartan-3a dsp fpga family data sheet, Module 1: introduction and ordering information, Module 2: functional description
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Table of contents
Document Outline
- Spartan-3A DSP FPGA Family Data Sheet
- Introduction and Ordering Information
- Functional Description
- DC and Switching Characteristics
- DC Electrical Characteristics
- Switching Characteristics
- Software Version Requirements
- I/O Timing
- Timing Measurement Methodology
- Using IBIS Models to Simulate Load Conditions in Application
- Simultaneously Switching Output Guidelines
- Configurable Logic Block (CLB) Timing
- Clock Buffer/Multiplexer Switching Characteristics
- Block RAM Timing
- DSP48A Timing
- Digital Clock Manager (DCM) Timing
- DNA Port Timing
- Suspend Mode Timing
- Configuration and JTAG Timing
- General Configuration Power-On/Reconfigure Timing
- Configuration Clock (CCLK) Characteristics
- Master Serial and Slave Serial Mode Timing
- Slave Parallel Mode Timing
- Serial Peripheral Interface (SPI) Configuration Timing
- Byte Peripheral Interface (BPI) Configuration Timing
- IEEE 1149.1/1532 JTAG Test Access Port Timing
- Revision History
- Pinout Descriptions