Rainbow Electronics MAX7473 - Manual (Page 10)

MAX7472/MAX7473
Early STOP Conditions
The MAX7472/MAX7473 recognize a STOP condition at
any point during transmission except when a STOP
condition occurs in the same high pulse as a START
condition (Figure 3). This condition is not a legal I
2 C
format; at least one clock pulse must separate any
START and STOP conditions. The MAX7472/MAX7473
discard any data received during a data transfer abort-
ed by an early STOP condition.
REPEATED START (Sr) Conditions
An Sr condition is used to indicate a change in direc-
tion of data flow (see the
Read Cycle section). Sr can
also be used when the bus master is writing to several
I
2 C devices and does not want to relinquish control of
the bus. The MAX7472/MAX7473 serial interface sup-
ports continuous write operations with (or without) an Sr
condition separating them.
Acknowledge Bit (ACK) and
Not-Acknowledge Bit (NACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX7472/MAX7473
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period
of the clock pulse (Figure 4). To generate a not acknowl-
edge, the receiver allows SDA to be pulled high before
the rising edge of the acknowledge-related clock pulse
(ninth pulse) and leaves it high during the high period of
the clock pulse. Monitoring the acknowledge bits allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the master should reattempt
communication at a later time.
The MAX7472/MAX7473 generate an acknowledge bit
when receiving an address or data by pulling SDA low
during the ninth clock pulse. When transmitting data
during a read, the MAX7472/MAX7473 do not drive
SDA during the ninth clock pulse (i.e., the external
pullups define the bus as a logic high) so that the
receiver of the data can pull SDA low to acknowledge
receipt of data.
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by the 7-bit slave
address (Figure 5). When idle, the MAX7472/MAX7473
wait for a START condition followed by its slave address.
The serial interface compares each address bit by bit,
allowing the interface to power down and disconnect
from SCL immediately if an incorrect address is detect-
ed. After recognizing a START condition followed by the
correct address, the MAX7472/MAX7473 are ready to
accept or send data. The least significant bit (LSB) of the
address byte (R/W) determines whether the master is
writing to or reading from the MAX7472/MAX7473 (R/W =
0 selects a write condition, R/W = 1 selects a read condi-
HDTV Anti-Aliasing Filters with Triple-Input Mux
10 ______________________________________________________________________________________
SCL
SDA
S P Sr
START
START STOP
ILLEGAL
STOP
LEGAL STOP CONDITION ILLEGAL STOP CONDITION
SCL
SDA
SCL
SDA
Figure 2. START/STOP Conditions
Figure 3. Early STOP Conditions
1 8 9
S
SDA
SCL
NOT ACKNOWLEDGE
ACKNOWLEDGE
Figure 4. Acknowledge and Not-Acknowledge Bits