Document Outline

• Features
• 1. Pin Configurations
  • 1.1 Pin Descriptions
• 2. Overview
  • 2.1 Block Diagram
  • 2.2 Automotive Quality Grade
  • 2.3 Pin Descriptions
    • 2.3.1 VCC
    • 2.3.2 GND
    • 2.3.3 Port B (PB7..PB0)
    • 2.3.4 Port C (PC7..PC0)
    • 2.3.5 Port D (PD7..PD0)
    • 2.3.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2
    • 2.3.7 AVCC
    • 2.3.8 AREF
  • 2.4 About Code Examples
• 3. AVR CPU Core
  • 3.1 Introduction
  • 3.2 Architectural Overview
  • 3.3 ALU - Arithmetic Logic Unit
  • 3.4 Status Register
  • 3.5 General Purpose Register File
    • 3.5.1 The X-register, Y-register, and Z-register
  • 3.6 Stack Pointer
  • 3.7 Instruction Execution Timing
  • 3.8 Reset and Interrupt Handling
    • 3.8.1 Interrupt Behavior
    • 3.8.2 Interrupt Response Time
• 4. Memories
  • 4.1 In-System Reprogrammable Flash Program Memory
  • 4.2 SRAM Data Memory
    • 4.2.1 SRAM Data Access Times
  • 4.3 EEPROM Data Memory
    • 4.3.1 EEPROM Read/Write Access
    • 4.3.2 The EEPROM Address Registers - EEARH and EEARL
    • 4.3.3 The EEPROM Data Register - EEDR
    • 4.3.4 The EEPROM Control Register - EECR
    • 4.3.5 Preventing EEPROM Corruption
  • 4.4 I/O Memory
  • 4.5 General Purpose I/O Registers
    • 4.5.1 General Purpose I/O Register 0 - GPIOR0
    • 4.5.2 General Purpose I/O Register 1 - GPIOR1
    • 4.5.3 General Purpose I/O Register 2 - GPIOR2
• 5. System Clock
  • 5.1 Clock Systems and their Distribution
    • 5.1.1 CPU Clock - clkCPU
    • 5.1.2 I/O Clock - clkI/O
    • 5.1.3 Flash Clock - clkFLASH
    • 5.1.4 PLL Clock - clkPLL
    • 5.1.5 ADC Clock - clkADC
  • 5.2 Clock Sources
  • 5.3 Default Clock Source
  • 5.4 Low Power Crystal Oscillator
  • 5.5 Calibrated Internal RC Oscillator
    • 5.5.1 Oscillator Calibration Register - OSCCAL
  • 5.6 PLL
    • 5.6.1 Internal PLL
    • 5.6.2 PLL Control and Status Register - PLLCSR
  • 5.7 128 kHz Internal Oscillator
  • 5.8 External Clock
  • 5.9 Clock Output Buffer
  • 5.10 System Clock Prescaler
    • 5.10.1 Clock Prescaler Register - CLKPR
• 6. Power Management and Sleep Modes
  • 6.1 Sleep Mode Control Register
    • 6.1.1 Sleep Mode Control Register - SMCR
  • 6.2 Idle Mode
  • 6.3 ADC Noise Reduction Mode
  • 6.4 Power-down Mode
  • 6.5 Standby Mode
  • 6.6 Power Reduction Register
    • 6.6.1 Power Reduction Register - PRR
  • 6.7 Minimizing Power Consumption
    • 6.7.1 Analog to Digital Converter
    • 6.7.2 Analog Comparator
    • 6.7.3 Brown-out Detector
    • 6.7.4 Internal Voltage Reference
    • 6.7.5 Watchdog Timer
    • 6.7.6 Port Pins
    • 6.7.7 On-chip Debug System
• 7. System Control and Reset
  • 7.1 Resetting the AVR
  • 7.2 Reset Sources
    • 7.2.1 Power-on Reset
    • 7.2.2 External Reset
    • 7.2.3 Brown-out Detection
    • 7.2.4 Watchdog Reset
    • 7.2.5 MCU Status Register - MCUSR
  • 7.3 Internal Voltage Reference
    • 7.3.1 Voltage Reference Enable Signals and Start-up Time
    • 7.3.2 Voltage Reference Characteristics
  • 7.4 Watchdog Timer
    • 7.4.1 Watchdog Timer Control Register - WDTCSR
• 8. Interrupts
  • 8.1 Interrupt Vectors in ATmega32/64/M1/C1
    • 8.1.1 Moving Interrupts Between Application and Boot Space
    • 8.1.2 MCU Control Register - MCUCR
• 9. I/O-Ports
  • 9.1 Introduction
  • 9.2 Ports as General Digital I/O
    • 9.2.1 Configuring the Pin
    • 9.2.2 Toggling the Pin
    • 9.2.3 Switching Between Input and Output
    • 9.2.4 Reading the Pin Value
    • 9.2.5 Digital Input Enable and Sleep Modes
  • 9.3 Alternate Port Functions
    • 9.3.1 MCU Control Register - MCUCR
    • 9.3.2 Alternate Functions of Port B
    • 9.3.3 Alternate Functions of Port C
    • 9.3.4 Alternate Functions of Port D
    • 9.3.5 Alternate Functions of Port E
  • 9.4 Register Description for I/O-Ports
    • 9.4.1 Port B Data Register - PORTB
    • 9.4.2 Port B Data Direction Register - DDRB
    • 9.4.3 Port B Input Pins Address - PINB
    • 9.4.4 Port C Data Register - PORTC
    • 9.4.5 Port C Data Direction Register - DDRC
    • 9.4.6 Port C Input Pins Address - PINC
    • 9.4.7 Port D Data Register - PORTD
    • 9.4.8 Port D Data Direction Register - DDRD
    • 9.4.9 Port D Input Pins Address - PIND
    • 9.4.10 Port E Data Register - PORTE
    • 9.4.11 Port E Data Direction Register - DDRE
    • 9.4.12 Port E Input Pins Address - PINE
• 10. External Interrupts
  • 10.1 Pin Change Interrupt Timing
  • 10.2 External Interrupt Control Register A - EICRA
    • 10.2.1 External Interrupt Mask Register - EIMSK
    • 10.2.2 External Interrupt Flag Register - EIFR
    • 10.2.3 Pin Change Interrupt Control Register - PCICR
    • 10.2.4 Pin Change Interrupt Flag Register - PCIFR
    • 10.2.5 Pin Change Mask Register 3 - PCMSK3
    • 10.2.6 Pin Change Mask Register 2 - PCMSK2
    • 10.2.7 Pin Change Mask Register 1 - PCMSK1
    • 10.2.8 Pin Change Mask Register 0 - PCMSK0
• 11. Timer/Counter0 and Timer/Counter1 Prescalers
  • 11.1 Internal Clock Source
  • 11.2 Prescaler Reset
  • 11.3 External Clock Source
    • 11.3.1 General Timer/Counter Control Register - GTCCR
• 12. 8-bit Timer/Counter0 with PWM
  • 12.1 Overview
    • 12.1.1 Definitions
    • 12.1.2 Registers
  • 12.2 Timer/Counter Clock Sources
  • 12.3 Counter Unit
  • 12.4 Output Compare Unit
    • 12.4.1 Force Output Compare
    • 12.4.2 Compare Match Blocking by TCNT0 Write
    • 12.4.3 Using the Output Compare Unit
  • 12.5 Compare Match Output Unit
    • 12.5.1 Compare Output Mode and Waveform Generation
  • 12.6 Modes of Operation
    • 12.6.1 Normal Mode
    • 12.6.2 Clear Timer on Compare Match (CTC) Mode
    • 12.6.3 Fast PWM Mode
    • 12.6.4 Phase Correct PWM Mode
  • 12.7 Timer/Counter Timing Diagrams
  • 12.8 8-bit Timer/Counter Register Description
    • 12.8.1 Timer/Counter Control Register A - TCCR0A
    • 12.8.2 Timer/Counter Control Register B - TCCR0B
    • 12.8.3 Timer/Counter Register - TCNT0
    • 12.8.4 Output Compare Register A - OCR0A
    • 12.8.5 Output Compare Register B - OCR0B
    • 12.8.6 Timer/Counter Interrupt Mask Register - TIMSK0
    • 12.8.7 Timer/Counter 0 Interrupt Flag Register - TIFR0
• 13. 16-bit Timer/Counter1 with PWM
  • 13.1 Overview
    • 13.1.1 Registers
    • 13.1.2 Definitions
  • 13.2 Accessing 16-bit Registers
    • 13.2.1 Reusing the Temporary High Byte Register
  • 13.3 Timer/Counter Clock Sources
  • 13.4 Counter Unit
  • 13.5 Input Capture Unit
    • 13.5.1 Input Capture Trigger Source
    • 13.5.2 Noise Canceler
    • 13.5.3 Using the Input Capture Unit
    • 13.5.4 Using the Input Capture Unit as TCNT1 Retrigger Input
  • 13.6 Output Compare Units
    • 13.6.1 Force Output Compare
    • 13.6.2 Compare Match Blocking by TCNTn Write
    • 13.6.3 Using the Output Compare Unit
  • 13.7 Compare Match Output Unit
    • 13.7.1 Compare Output Mode and Waveform Generation
  • 13.8 Modes of Operation
    • 13.8.1 Normal Mode
    • 13.8.2 Clear Timer on Compare Match (CTC) Mode
    • 13.8.3 Fast PWM Mode
    • 13.8.4 Phase Correct PWM Mode
    • 13.8.5 Phase and Frequency Correct PWM Mode
  • 13.9 Timer/Counter Timing Diagrams
  • 13.10 16-bit Timer/Counter Register Description
    • 13.10.1 Timer/Counter1 Control Register A - TCCR1A
    • 13.10.2 Timer/Counter1 Control Register B - TCCR1B
    • 13.10.3 Timer/Counter1 Control Register C - TCCR1C
    • 13.10.4 Timer/Counter1 - TCNT1H and TCNT1L
    • 13.10.5 Output Compare Register 1 A - OCR1AH and OCR1AL
    • 13.10.6 Output Compare Register 1 B - OCR1BH and OCR1BL
    • 13.10.7 Input Capture Register 1 - ICR1H and ICR1L
    • 13.10.8 Timer/Counter1 Interrupt Mask Register - TIMSK1
    • 13.10.9 Timer/Counter1 Interrupt Flag Register - TIFR1
• 14. Power Stage Controller - (PSC) (only ATmega32/64M1)
  • 14.1 Features
  • 14.2 Overview
  • 14.3 Accessing 16-bit Registers
  • 14.4 PSC Description
  • 14.5 Functional Description
    • 14.5.1 Generation of Control Waveforms
    • 14.5.2 Waveform Cycles
    • 14.5.3 Operation Mode Descriptions
      • 14.5.3.1 One Ramp Mode (Edge-Aligned)
      • 14.5.3.2 Center Aligned Mode
  • 14.6 Update of Values
    • 14.6.1 Value Update Synchronization
  • 14.7 Overlap Protection
  • 14.8 Signal Description
    • 14.8.1 Input Description
    • 14.8.2 Output Description
  • 14.9 PSC Input
    • 14.9.1 PSC Input Configuration
      • 14.9.1.1 Filter Enable
      • 14.9.1.2 Signal Polarity
      • 14.9.1.3 Input Mode Operation
  • 14.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.
  • 14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
  • 14.12 Analog Synchronization
  • 14.13 Interrupt Handling
  • 14.14 PSC Clock Sources
  • 14.15 Interrupts
    • 14.15.1 Interrupt Vector
    • 14.15.2 PSC Interrupt Vectors in ATmega32/64/M1/C1
  • 14.16 PSC Register Definition
    • 14.16.1 PSC Output Configuration - POC
    • 14.16.2 PSC Synchro Configuration - PSYNC
    • 14.16.3 PSC Output Compare SA Register - POCRnSAH and POCRnSAL
    • 14.16.4 PSC Output Compare RA Register - POCRnRAH and POCRnRAL
    • 14.16.5 PSCOutput Compare SB Register - POCRnSBH and POCRnSBL
    • 14.16.6 PSC Output Compare RB Register - POCR_RBH and POCR_RBL
    • 14.16.7 PSC Configuration Register - PCNF
    • 14.16.8 PSC Control Register - PCTL
    • 14.16.9 PSC Module n Input Control Register - PMICn
    • 14.16.10 PSC Interrupt Mask Register - PIM
    • 14.16.11 PSC Interrupt Flag Register - PIFR
• 15. Serial Peripheral Interface - SPI
  • 15.1 Features
  • 15.2 SS Pin Functionality
    • 15.2.1 Slave Mode
    • 15.2.2 Master Mode
    • 15.2.3 MCU Control Register - MCUCR
    • 15.2.4 SPI Control Register - SPCR
    • 15.2.5 SPI Status Register - SPSR
    • 15.2.6 SPI Data Register - SPDR
  • 15.3 Data Modes
• 16. Controller Area Network - CAN
  • 16.1 Features
  • 16.2 CAN Protocol
    • 16.2.1 Principles
    • 16.2.2 Message Formats
      • 16.2.2.1 Can Standard Frame
      • 16.2.2.2 CAN Extended Frame
      • 16.2.2.3 Format Co-existence
    • 16.2.3 CAN Bit Timing
      • 16.2.3.1 Bit Construction
      • 16.2.3.2 Synchronization Segment
      • 16.2.3.3 Propagation Time Segment
      • 16.2.3.4 Phase Segment 1
      • 16.2.3.5 Sample Point
      • 16.2.3.6 Phase Segment 2
      • 16.2.3.7 Information Processing Time
      • 16.2.3.8 Bit Lengthening
      • 16.2.3.9 Bit Shortening
      • 16.2.3.10 Synchronization Jump Width
      • 16.2.3.11 Programming the Sample Point
      • 16.2.3.12 Synchronization
    • 16.2.4 Arbitration
    • 16.2.5 Errors
      • 16.2.5.1 Error at Message Level
      • 16.2.5.2 Error at Bit Level
      • 16.2.5.3 Error Signalling
  • 16.3 CAN Controller
  • 16.4 CAN Channel
    • 16.4.1 Configuration
    • 16.4.2 Bit Timing
    • 16.4.3 Baud Rate
    • 16.4.4 Fault Confinement
    • 16.4.5 Overload Frame
  • 16.5 Message Objects
    • 16.5.1 Number of MObs
    • 16.5.2 Operating Modes
      • 16.5.2.1 Disabled
      • 16.5.2.2 Tx Data & Remote Frame
      • 16.5.2.3 Rx Data & Remote Frame
      • 16.5.2.4 Automatic Reply
      • 16.5.2.5 Frame Buffer Receive Mode
    • 16.5.3 Acceptance Filter
    • 16.5.4 MOb Page
    • 16.5.5 CAN Data Buffers
  • 16.6 CAN Timer
    • 16.6.1 Prescaler
    • 16.6.2 16-bit Timer
    • 16.6.3 Time Triggering
    • 16.6.4 Stamping Message
  • 16.7 Error Management
    • 16.7.1 Fault Confinement
    • 16.7.2 Error Types
    • 16.7.3 Error Setting
  • 16.8 Interrupts
    • 16.8.1 Interrupt organization
    • 16.8.2 Interrupt Behavior
  • 16.9 CAN Register Description
  • 16.10 General CAN Registers
    • 16.10.1 CAN General Control Register - CANGCON
    • 16.10.2 CAN General Status Register - CANGSTA
    • 16.10.3 CAN General Interrupt Register - CANGIT
    • 16.10.4 CAN General Interrupt Enable Register - CANGIE
    • 16.10.5 CAN Enable MOb Registers - CANEN2 and CANEN1
    • 16.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1
    • 16.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
    • 16.10.8 CAN Bit Timing Register 1 - CANBT1
    • 16.10.9 CAN Bit Timing Register 2 - CANBT2
    • 16.10.10 CAN Bit Timing Register 3 - CANBT3
    • 16.10.11 CAN Timer Control Register - CANTCON
    • 16.10.12 CAN Timer Registers - CANTIML and CANTIMH
    • 16.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH
    • 16.10.14 CAN Transmit Error Counter Register - CANTEC
    • 16.10.15 CAN Receive Error Counter Register - CANREC
    • 16.10.16 CAN Highest Priority MOb Register - CANHPMOB
    • 16.10.17 CAN Page MOb Register - CANPAGE
  • 16.11 MOb Registers
    • 16.11.1 CAN MOb Status Register - CANSTMOB
    • 16.11.2 CAN MOb Control and DLC Register - CANCDMOB
    • 16.11.3 CAN Identifier Tag Registers - CANIDT1, CANIDT2, CANIDT3, and CANIDT4
    • 16.11.4 CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4
    • 16.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH
    • 16.11.6 CAN Data Message Register - CANMSG
  • 16.12 Examples of CAN Baud Rate Setting
• 17. LIN / UART - Local Interconnect Network Controller or UART
  • 17.1 LIN Features
  • 17.2 UART Features
  • 17.3 LIN Protocol
    • 17.3.1 Master and Slave
    • 17.3.2 Frames
    • 17.3.3 Data Transport
    • 17.3.4 Schedule Table
    • 17.3.5 Compatibility with LIN 1.3
  • 17.4 LIN / UART Controller
    • 17.4.1 LIN Overview
    • 17.4.2 UART Overview
    • 17.4.3 LIN/UART Controller Structure
    • 17.4.4 LIN/UART Command Overview
    • 17.4.5 Enable / Disable
    • 17.4.6 LIN Commands
      • 17.4.6.1 Rx Header / LIN Abort Function
      • 17.4.6.2 Tx Header Function
      • 17.4.6.3 Rx & TX Response Functions
      • 17.4.6.4 Handling Data of LIN response
    • 17.4.7 UART Commands
      • 17.4.7.1 Data Handling
      • 17.4.7.2 Rx Service
      • 17.4.7.3 Tx Service
  • 17.5 LIN / UART Description
    • 17.5.1 Reset
    • 17.5.2 Clock
    • 17.5.3 LIN Protocol Selection
    • 17.5.4 Configuration
    • 17.5.5 Busy Signal
      • 17.5.5.1 Busy Signal in LIN Mode
      • 17.5.5.2 Busy Signal in UART Mode
    • 17.5.6 Bit Timing
      • 17.5.6.1 Baud rate Generator
      • 17.5.6.2 Re-synchronization in LIN Mode
      • 17.5.6.3 Handling LBT[5..0]
    • 17.5.7 Data Length
      • 17.5.7.1 Data Length in LIN 2.1
      • 17.5.7.2 Data Length in LIN 1.3
      • 17.5.7.3 Data Length in Rx Response
      • 17.5.7.4 Data Length in Tx Response
      • 17.5.7.5 Data Length after Error
      • 17.5.7.6 Data Length in UART Mode
    • 17.5.8 xxOK Flags
    • 17.5.9 xxERR Flags
    • 17.5.10 Frame Time Out
    • 17.5.11 Break-in-data
    • 17.5.12 Checksum
    • 17.5.13 Interrupts
    • 17.5.14 Message Filtering
    • 17.5.15 Data Management
      • 17.5.15.1 LIN FIFO Data Buffer
      • 17.5.15.2 UART Data Register
    • 17.5.16 OCD Support
  • 17.6 LIN / UART Register Description
    • 17.6.1 LIN Control Register - LINCR
    • 17.6.2 LIN Status and Interrupt Register - LINSIR
    • 17.6.3 LIN Enable Interrupt Register - LINENIR
    • 17.6.4 LIN Error Register - LINERR
    • 17.6.5 LIN Bit Timing Register - LINBTR
    • 17.6.6 LIN Baud Rate Register - LINBRR
    • 17.6.7 LIN Data Length Register - LINDLR
    • 17.6.8 LIN Identifier Register - LINIDR
    • 17.6.9 LIN Data Buffer Selection Register - LINSEL
    • 17.6.10 LIN Data Register - LINDAT
• 18. Analog to Digital Converter - ADC
  • 18.1 Features
  • 18.2 Operation
  • 18.3 Starting a Conversion
  • 18.4 Prescaling and Conversion Timing
  • 18.5 Changing Channel or Reference Selection
    • 18.5.1 ADC Input Channels
    • 18.5.2 ADC Voltage Reference
  • 18.6 ADC Noise Canceler
    • 18.6.1 Analog Input Circuitry
    • 18.6.2 Analog Noise Canceling Techniques
    • 18.6.3 Offset Compensation Schemes
    • 18.6.4 ADC Accuracy Definitions
  • 18.7 ADC Conversion Result
  • 18.8 Temperature Measurement
    • 18.8.1 User Calibration
    • 18.8.2 Manufacturing Calibration
  • 18.9 ADC Register Description
    • 18.9.1 ADC Multiplexer Register - ADMUX
    • 18.9.2 ADC Control and Status Register A - ADCSRA
    • 18.9.3 ADC Control and Status Register B- ADCSRB
    • 18.9.4 ADC Result Data Registers - ADCH and ADCL
      • 18.9.4.1 ADLAR = 0
      • 18.9.4.2 ADLAR = 1
    • 18.9.5 Digital Input Disable Register 0 - DIDR0
    • 18.9.6 Digital Input Disable Register 1- DIDR1
  • 18.10 Amplifier
  • 18.11 Amplifier Control Registers
    • 18.11.1 Amplifier 0 Control and Status register - AMP0CSR
    • 18.11.2 Amplifier 1 Control and Status register - AMP1CSR
    • 18.11.3 Amplifier 2 Control and Status register - AMP2CSR
• 19. ISRC - Current Source
  • 19.1 Features
  • 19.2 Typical applications
    • 19.2.1 LIN Current Source
    • 19.2.2 Voltage Reference for External Devices
    • 19.2.3 Threshold Reference for Internal Analog Comparator
  • 19.3 Control Register
    • 19.3.1 ADC Control and Status Register B- ADCSRB
• 20. Analog Comparator
  • 20.1 Features
  • 20.2 Overview
  • 20.3 Use of ADC Amplifiers
  • 20.4 Analog Comparator Register Description
    • 20.4.1 Analog Comparator 0 Control Register - AC0CON
    • 20.4.2 Analog Comparator 1Control Register - AC1CON
    • 20.4.3 Analog Comparator 2 Control Register - AC2CON
    • 20.4.4 Analog Comparator 3 Control Register - AC3CON
    • 20.4.5 Analog Comparator Status Register - ACSR
    • 20.4.6 Digital Input Disable Register 0 - DIDR0
    • 20.4.7 Digital Input Disable Register 1- DIDR1
• 21. Digital to Analog Converter - DAC
  • 21.1 Features
  • 21.2 Operation
  • 21.3 Starting a Conversion
    • 21.3.1 DAC Voltage Reference
  • 21.4 DAC Register Description
    • 21.4.1 Digital to Analog Conversion Control Register - DACON
    • 21.4.2 Digital to Analog Converter input Register - DACH and DACL
      • 21.4.2.1 DALA = 0
      • 21.4.2.2 DALA = 1
• 22. debugWIRE On-chip Debug System
  • 22.1 Features
  • 22.2 Overview
  • 22.3 Physical Interface
  • 22.4 Software Break Points
  • 22.5 Limitations of debugWIRE
  • 22.6 debugWIRE Related Register in I/O Memory
    • 22.6.1 debugWire Data Register - DWDR
• 23. Boot Loader Support - Read-While-Write Self-Programming ATmega32/64/M1/C1
  • 23.1 Boot Loader Features
  • 23.2 Application and Boot Loader Flash Sections
    • 23.2.1 Application Section
    • 23.2.2 BLS - Boot Loader Section
  • 23.3 Read-While-Write and No Read-While-Write Flash Sections
    • 23.3.1 RWW - Read-While-Write Section
    • 23.3.2 NRWW - No Read-While-Write Section
  • 23.4 Boot Loader Lock Bits
  • 23.5 Entering the Boot Loader Program
    • 23.5.1 Store Program Memory Control and Status Register - SPMCSR
  • 23.6 Addressing the Flash During Self-Programming
  • 23.7 Self-Programming the Flash
    • 23.7.1 Performing Page Erase by SPM
    • 23.7.2 Filling the Temporary Buffer (Page Loading)
    • 23.7.3 Performing a Page Write
    • 23.7.4 Using the SPM Interrupt
    • 23.7.5 Consideration While Updating BLS
    • 23.7.6 Prevent Reading the RWW Section During Self-Programming
    • 23.7.7 Setting the Boot Loader Lock Bits by SPM
    • 23.7.8 EEPROM Write Prevents Writing to SPMCSR
    • 23.7.9 Reading the Fuse and Lock Bits from Software
    • 23.7.10 Reading the Signature Row from Software
    • 23.7.11 Preventing Flash Corruption
    • 23.7.12 Programming Time for Flash when Using SPM
    • 23.7.13 Simple Assembly Code Example for a Boot Loader
    • 23.7.14 ATmega32/64/M1/C1 - 32K -Flash Boot Loader Parameters
    • 23.7.15 ATmega32/64/M1/C1 - 64K - Flash Boot Loader Parameters
• 24. Memory Programming
  • 24.1 Program And Data Memory Lock Bits
  • 24.2 Fuse Bits
  • 24.3 PSC Output Behavior During Reset
    • 24.3.1 Latching of Fuses
  • 24.4 Signature Bytes
    • 24.4.1 Signature Bytes
  • 24.5 Calibration Byte
  • 24.6 Parallel Programming Parameters, Pin Mapping, and Commands
    • 24.6.1 Signal Names
  • 24.7 Serial Programming Pin Mapping
  • 24.8 Parallel Programming
    • 24.8.1 Enter Programming Mode
    • 24.8.2 Considerations for Efficient Programming
    • 24.8.3 Chip Erase
    • 24.8.4 Programming the Flash
    • 24.8.5 Programming the EEPROM
    • 24.8.6 Reading the Flash
    • 24.8.7 Reading the EEPROM
    • 24.8.8 Programming the Fuse Low Bits
    • 24.8.9 Programming the Fuse High Bits
    • 24.8.10 Programming the Extended Fuse Bits
    • 24.8.11 Programming the Lock Bits
    • 24.8.12 Reading the Fuse and Lock Bits
    • 24.8.13 Reading the Signature Bytes
    • 24.8.14 Reading the Calibration Byte
    • 24.8.15 Parallel Programming Characteristics
  • 24.9 Serial Downloading
    • 24.9.1 Serial Programming Algorithm
    • 24.9.2 Data Polling Flash
    • 24.9.3 Data Polling EEPROM
    • 24.9.4 SPI Serial Programming Characteristics
• 25. Electrical Characteristics
  • 25.1 Absolute Maximum Ratings*
  • 25.2 DC Characteristics
  • 25.3 Clock Characteristics
    • 25.3.1 Calibrated Internal RC Oscillator Accuracy
  • 25.4 External Clock Drive Characteristics
  • 25.5 Maximum Speed vs. VCC
  • 25.6 PLL Characteristics
  • 25.7 SPI Timing Characteristics
  • 25.8 ADC Characteristics
  • 25.9 Parallel Programming Characteristics
• 26. ATmega32/64/M1/C1 Typical Characteristics
  • 26.1 Active Supply Current
  • 26.2 Idle Supply Current
    • 26.2.1 Using the Power Reduction Register
  • 26.3 Power-Down Supply Current
  • 26.4 Standby Supply Current
  • 26.5 Pin Pull-up
  • 26.6 Pin Driver Strength
  • 26.7 Pin Thresholds and Hysteresis
  • 26.8 BOD Thresholds and Analog Comparator Hysterisis
  • 26.9 Analog Reference
  • 26.10 Internal Oscillator Speed
  • 26.11 Current Consumption of Peripheral Units
  • 26.12 Current Consumption in Reset and Reset Pulse width
• 27. Register Summary
• 28. Instruction Set Summary
• 29. Errata
  • 29.1 Errata Summary
    • 29.1.1 ATmega32/64/M1/C1 Rev. A (Mask Revision)
  • 29.2 Errata Description
• 30. Ordering Information
• 31. Package Information
  • 31.1 TQFP32
  • 31.2 QFN32
• 32. Datasheet Revision History for ATmega32/64/M1/C1
  • 32.1 7647A