Rainbow Electronics AT45DB011D - Manual (Page 20)

20
3639J–DFLASH–11/2012
AT45DB011D
10.2.2 Reading the Security Register
The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, the con-
tent of the Security Register can be clocked out on the SO pins. After the last byte of the
Security Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins
into a high-impedance state.
Figure 10-4. Read Security Register
11. Additional Commands
11.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to the buffer. To start the operation for
the DataFlash standard page size (264-bytes), a 1-byte opcode, 53H, must be clocked into the
device, followed by three address bytes comprised of six don’t care bits, nine page address bits
(PA8 - PA0), which specify the page in main memory that is to be transferred, and nine don’t
care bits. To perform a main memory page to buffer transfer for the binary page size (256-
bytes), the opcode 53H must be clocked into the device followed by three address bytes consist-
ing of seven don’t care bits, nine page address bits (A16 - A8) which specify the page in the
main memory that is to be transferred, and eight don’t care bits. The CS pin must be low while
toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). The trans-
fer of the page of data from the main memory to the buffer will begin when the CS pin transitions
from a low to a high state. During the transfer of a page of data (t
XFR
), the status register can be
read to determine whether the transfer has been completed.
11.2 Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in the buffer. To initiate the opera-
tion for the DataFlash standard page size, a 1-byte opcode, 60H, must be clocked into the
device, followed by three address bytes consisting of six don’t care bits, nine page address bits
(PA8 - PA0) that specify the page in the main memory that is to be compared to the buffer, and
nine don’t care bits. To start a main memory page to buffer compare for a binary page size, the
opcode 60H must be clocked into the device followed by three address bytes consisting of six
don’t care bits, nine page address bits (A16 - A8) that specify the page in the main memory that
is to be compared to the buffer, and eight don’t care bits. The CS pin must be low while toggling
the SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high
transition of the CS pin, the data bytes in the selected main memory page will be compared with
the data bytes in the buffer. During this time (t
COMP
), the status register will indicate that the part
is busy. On completion of the compare operation, bit 6 of the status register is updated with the
result of the compare.
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + x
Each transition
represents 8 bits
SI
SO