Rainbow Electronics AT90LS4433 - Manual (Page 17)

17
AT90S/LS4433
1042G–AVR–09/02
Figure 23. On-chip Data SRAM Access Cycles
I/O Memory The I/O space definition of the AT90S4433 is shown in Table 2.
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read
Wr
ite
Table 2. AT90S4433 I/O Space
(1)
I/O Address
(SRAM Address) Name Function
$3F ($5F) SREG Status Register
$3D ($5D) SP Stack Pointer
$3B ($5B) GIMSK General Interrupt MaSK Register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK Register
$38 ($58) TIFR Timer/Counter Interrupt Flag Register
$35 ($55) MCUCR MCU general Control Register
$34 ($54) MCUSR MCU general Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
$2D ($4D) TCNT1H Timer/Counter1 High Byte
$2C ($4C) TCNT1L Timer/Counter1 Low Byte
$2B ($4B) OCR1H Timer/Counter1 Output Compare Register High Byte
$2A ($4A) OCR1L Timer/Counter1 Output Compare Register Low Byte
$27 ($47) ICR1H Timer/Counter1 Input Capture Register High Byte
$26 ($46) ICR1L Timer/Counter 1 Input Capture Register Low Byte
$21 ($41) WDTCR Watchdog Timer Control Register
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$18 ($38) PORTB Data Register, Port B