Rainbow Electronics AT90LS4433 - Manual (Page 41)

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AT90S/LS4433
1042G–AVR–09/02
Timer/Counter1 Input Capture
Register – ICR1H and ICR1L
The Input Capture Register is a 16-bit, read only register.
When the rising or falling edge (according to the input capture edge setting [ICES1]) of
the signal at the Input Capture Pin (ICP) is detected, the current value of the
Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,
the Input Capture Flag (ICF1) is set (one).
Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register
(TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously.
When the CPU reads the Low Byte, ICR1L, the data is sent to the CPU and the data of
the High Byte, ICR1H, is placed in the TEMP Register. When the CPU reads the data in
the High Byte, ICR1H, the CPU receives the data in the TEMP Register. Consequently,
the Low Byte, ICR1L, must be accessed first for a full 16-bit register read operation.
The TEMP Register is also used when accessing TCNT1 and OCR1. If the main pro-
gram and interrupt routines perform access to registers using TEMP, interrupts must be
disabled during access from the main program.
Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1
(OCR1) form a 8-, 9-, or 10-bit, free-running, glitch-free, phase correct PWM with output
on the PB1(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up from
$0000 to TOP (see Table 13), where it turns and counts down again to zero before the
cycle is repeated. When the counter value matches the contents of the 8, 9, or 10 least
significant bits of OCR1, the PB1(OC1) pin is set or cleared according to the settings of
the COM11 and COM10 bits in the Timer/Counter1 Control Register (TCCR1). Refer to
Table 14 for details.
Note: 1. If the Compare Register contains the TOP value and the prescaler is not in use
(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the
up-counting and down-counting values are reached simultaneously. When the pres-
caler is in use (CS12..CS10
≠ 001 or 000), the PWM output goes active when the
counter reaches the TOP value, but the down-counting compare match is not inter-
preted to be reached before the next time the counter reaches the TOP value,
making a one-period PWM pulse.
Bit 15 14 13 12 11 10 9 8
$27 ($47) MSB ICR1H
$26 ($46) LSB ICR1L
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R
R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Table 13. Timer TOP Values and PWM Frequency (1)
PWM Resolution Timer TOP Value Frequency
8-bit $00FF (255) f
TCK1
/510
9-bit $01FF (511) f
TCK1
/1022
10-bit $03FF(1023) f
TCK1
/2046