Rainbow Electronics AT90LS4433 - Manual (Page 56)

56
AT90S/LS4433
1042G–AVR–09/02
Multi-processor
Communication Mode The Multi-processor Communication mode enables several slave MCUs to receive data
from a Master MCU. This is done by first decoding an address byte to find out which
MCU has been addressed. If a particular slave MCU has been addressed, it will receive
the following data bytes as normal, while the other slave MCUs will ignore the data bytes
until another address byte is received.
For an MCU to act as a Master MCU, it should enter 9-bit Transmission mode (CHR9 in
UCSRB set). The ninth bit must be one to indicate that an address byte is being trans-
mitted, and zero to indicate that a data byte is being transmitted.
For the Slave MCUs, the mechanism appears slightly differently for 8-bit and 9-bit
Reception mode. In 8-bit Reception mode (CHR9 in UCSRB cleared), the stop bit is one
for an address byte and zero for a data byte. In 9-bit Reception mode (CHR9 in UCSRB
set), the ninth bit is one for an address byte and zero for a data byte, whereas the stop
bit is always high.
The following procedure should be used to exchange data in Multi-processor Communi-
cation mode:
1. All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA
is set).
2. The Master MCU sends an address byte, and all Slaves receive and read this
byte. In the slave MCUs, the RXC Flag in UCSRA will be set as normal.
3. Each Slave MCU reads the UDR Register and determines if it has been
selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next
address byte.
4. For each received data byte, the receiving MCU will set the Receive Complete
Flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a
Framing Error (FE in UCSRA set), since the stop bit is zero. The other Slave
MCUs, which still have the MPCM bit set, will ignore the data byte. In this case,
the UDR Register and the RXC or FE Flags will not be affected.
5. After the last byte has been transferred, the process repeats from step 2.