Rainbow Electronics DS3134 - Manual (Page 13)

DS3134
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DS3134 RESTRICTIONS FOR REV B1/B2 SILICON Table 1D
Port maximum of 16 channelized and unchannelized physical ports
Unchannelized ports 0 & 1: maximum data rate of 52 Mbps
port 2 to 15: maximum data rate of 10 Mbps
Channelized Channelized and with frame interleave interfaces or a minimum of
two/multiple of two consecutive DS0 time slot assigned to one
HDLC channel:
40 T1/E1 channels
Channelized Channelized and with byte interleave interfaces:
32 T1/E1 channels
Throughput maximum receive: 104 Mbps
maximum transmit: 104 Mbps
HDLC maximum of 256 channels
if the Fast HDLC Engine on Port 0 is being used, then it must be
HDLC Channel 1*
if the Fast HDLC Engine on Port 1 is being used, then it must be
HDLC Channel 2*
* The 256 HDLC channels within the device are numbered from 1 to 256.
INTERNAL DEVICE CONFIGURATION REGISTERS
All of the internal device configuration registers (with the exception of the PCI Configuration Registers
which are 32-bit registers) are 16 bits wide and they are not byte addressable. When the Host on the PCI
Bus accesses these registers, the particular combination of byte enables (i.e. PCBE* signals) is not
important but at least one of the byte enables must be asserted for a transaction to occur. All the registers
are read/write registers unless otherwise noted. Not assigned bits (identified as n/a in the data sheet)
should be set to zero when written to allow for future upgrades to the device. These bits have no meaning
and could be either zero or one when read.