Rainbow Electronics DS3134 - Manual (Page 97)

DS3134
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DMA Registers that must be configured by the Host on Power-Up Table 8.0A
Address Acronym Register Section
0700 RFQBA0 Receive Free Queue Base Address 0 (lower word). 8.1.3
0704 RFQBA1 Receive Free Queue Base Address 1 (upper word). 8.1.3
0708 RFQEA Receive Free Queue End Address. 8.1.3
070C RFQSBSA Receive Free Queue Small Buffer Start Address. 8.1.3
0710 RFQLBWP Receive Free Queue Large Buffer Host Write Pointer. 8.1.3
0714 RFQSBWP Receive Free Queue Small Buffer Host Write Pointer. 8.1.3
0718 RFQLBRP Receive Free Queue Large Buffer DMA Read Pointer. 8.1.3
071C RFQSBRP Receive Free Queue Small Buffer DMA Read Pointer. 8.1.3
0730 RDQBA0 Receive Done Queue Base Address 0 (lower word). 8.1.4
0734 RDQBA1 Receive Done Queue Base Address 1 (upper word). 8.1.4
0738 RDQEA Receive Done Queue End Address. 8.1.4
073C RDQRP Receive Done Queue Host Read Pointer. 8.1.4
0740 RDQWP Receive Done Queue DMA Write Pointer. 8.1.4
0744 RDQFFT Receive Done Queue FIFO Flush Timer. 8.1.4
0750 RDBA0 Receive Descriptor Base Address 0 (lower word). 8.1.2
0754 RDBA1 Receive Descriptor Base Address 1 (upper word). 8.1.2
0770 RDMACIS Receive DMA Configuration Indirect Select. 8.1.5
0774 RDMAC Receive DMA Configuration (all 256 channels). 8.1.5
0780 RDMAQ Receive DMA Queues Control. 8.1.3/.4
0790 RLBS Receive Large Buffer Size. 8.1.1
0794 RSBS Receive Small Buffer Size. 8.1.1
0800 TPQBA0 Transmit Pending Queue Base Address 0 (lower word). 8.2.3
0804 TPQBA1 Transmit Pending Queue Base Address 1 (upper word). 8.2.3
0808 TPQEA Transmit Pending Queue End Address. 8.2.3
080C TPQWP Transmit Pending Queue Host Write Pointer. 8.2.3
0810 TPQRP Transmit Pending Queue DMA Read Pointer. 8.2.3
0830 TDQBA0 Transmit Done Queue Base Address 0 (lower word). 8.2.4
0834 TDQBA1 Transmit Done Queue Base Address 1 (upper word). 8.2.4
0838 TDQEA Transmit Done Queue End Address. 8.2.4
083C TDQRP Transmit Done Queue Host Read Pointer. 8.2.4
0840 TDQWP Transmit Done Queue DMA Write Pointer. 8.2.4
0844 TDQFFT Transmit Done Queue FIFO Flush Timer. 8.2.4
0850 TDBA0 Transmit Descriptor Base Address 0 (lower word). 8.2.2
0854 TDBA1 Transmit Descriptor Base Address 1 (upper word). 8.2.2
0870 TDMACIS Transmit DMA Configuration Indirect Select. 8.2.5
0874 TDMAC Transmit DMA Configuration (all 256 channels). 8.2.5
0880 TDMAQ Transmit Queues FIFO Control. 8.2.3/.4