Rainbow Electronics AT25DQ321 - Manual (Page 7)

7 AT25DQ321 [DATASHEET]
8718D–DFLASH–12/2012
5. Device Operation
The AT25DQ321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25DQ321 via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DQ321 supports
the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the
SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI
Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
5.1 Dual-I/O and Quad-I/O Operation
The AT25DQ321 features a Dual-Input Program mode and a Dual-Output Read mode that allows two bits of data to be
clocked into or out of the device every clock cycle to improve throughputs. To accomplish this, both the SI and SO pins
are utilized as inputs/outputs for the transfer of data bytes. With the Dual-Input Byte/Page Program command, the the SO
pin becomes an input along with the SI pin. Alternatively, with the Dual-Output Read Array command, the SI pin becomes
an output along with the SO pin. For both Dual-I/O commands, the SO pin will be referred to as I/O
1
and the SI pin will be
referred to as I/O
0
.
The device also supports a Quad-Input Program mode and a Quad-Output Read mode in which the WP and HOLD pins
become data pins for even higher throughputs. For the Quad-Input Byte/Page Program command and for the
Quad-Output Read Array command, the HOLD, WP, SO, and SI pins are referred to as I/O
3-0
where HOLD becomes I/O
3
,
WP becomes I/O
2
, SO becomes I/O
1
, and SI becomes I/O
0
. The QE bit in the Configuration Register must be set in order
for both Quad-I/O commands to be enabled and for the HOLD and WP pins to be converted to I/O data pins.
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the Most-Significant Bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DQ321 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then
reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device,
then no operation will be performed and the device will simply return to the idle state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since
the upper address limit of the AT25DQ321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by the
device.
SO
SI
SCK
CS
MSB LSB
MSB LSB