2 dual-output read array, Sck cs si (sio) so (soi) – Rainbow Electronics AT25DL161 User Manual
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AT25DL161 [DATASHEET]
8795E–DFLASH–12/2012
7.2
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by f
RDDO
. To
perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SIO pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit 7 of the first data byte is output on the SO pin, while bit 6 of the same data
byte is output on the SIO pin. During the next clock cycle, bits 5 and 4 of the first data byte are output on the SO and SIO
pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the
last byte (1FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The
CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4. Dual-Output Read Array
SCK
CS
SI (SIO)
SO (SOI)
MSB
MSB
2
3
1
0
0
0
1
1
1
0
1
1
6
7
5
4
10 11
9
8
12
39
42 43
41
40
37 38
33
36
35
34
31 32
29 30
44
47 48
46
45
Opcode
A
A
A
A
A
A
A
A
A
MSB
X
X
X
X
X
X
X
X
MSB
MSB
MSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
D3
D2
D1
D0
Address Bits A23-A0
Don't Care
Output
Data Byte 1
Output
Data Byte 2
High-impedance