Rainbow Electronics AT45DB021D - Manual (Page 14)

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3638K–DFLASH–11/2012
AT45DB021D
guaranteed. Furthermore, if more than 8-bytes of data is clocked into the device, then the data will wrap back
around to the beginning of the register. For instance, if 9-bytes of data are clocked in, then the ninth byte will be
stored at byte location zero of the Sector Protection Register.
If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register, then the
protection status of the sector corresponding to that byte location cannot be guaranteed. For example, if a value of
17H is clocked into byte location two of the Sector Protection Register, then the protection status of sector two
cannot be guaranteed.
The Sector Protection Register can be reprogrammed while the sector protection enabled or disabled. Being able
to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily
disable the sector protection to an individual sector rather than disabling sector protection completely.
The Program Sector Protection Register command utilizes the internal SRAM buffer for processing. Therefore, the
contents of the buffer will be altered from its previous state when this command is issued.
Table 7-5. Program Sector Protection Register Command
Figure 7-3. Program Sector Protection Register
7.1.3 Read Sector Protection Register Command
To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an
opcode of 32H and three dummy bytes must be clocked in via the SI pin. After the last bit of the opcode and
dummy bytes have been clocked in, any additional clock pulses on the SCK pins will result in data for the content
of the Sector Protection Register being output on the SO pin. The first byte corresponds to sector 0 (0a, 0b), the
second byte corresponds to sector one, the third byte corresponds to sector two, and the last byte (byte four)
corresponds to sector three. Once the last byte of the Sector Protection Register has been clocked out, any
additional clock pulses will result in undefined data being output on the SO pin. The CS must be deasserted to
terminate the Read Sector Protection Register operation and put the output into a high-impedance state.
Table 7-6. Read Sector Protection Register Command
Note: xx = Dummy Byte
Figure 7-4. Read Sector Protection Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Program Sector Protection Register 3DH 2AH 7FH FCH
Data Byte
n
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n + 1
Data Byte
n + 3
CS
Each transition
represents 8 bits
SI
Command Byte 1 Byte 2 Byte 3 Byte 4
Read Sector Protection Register 32H xxH xxH xxH
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + 3
SI
SO
Each transition
represents 8 bits