Rainbow Electronics HT49R70A-1 - Manual (Page 13)

HT49R70A-1
Rev. 1.00 13 December 4, 2001
The WDT time-out period is fixed as f
S
/2 16 .
If the WDT clock source chooses the internal WDT oscil-
lator, the time-out period may vary with temperature,
VDD, and process variations. On the other hand, if the
clock source selects the instruction clock and the
²HALT² instruction is executed, WDT may stop counting
and lose its protecting purpose, and the logic can only
be restarted by an external logic.
When the device operates in a noisy environment, using
the on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT can stop the system clock.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a
²warm reset², and only
the PC and SP are reset to zero. To clear the contents of
the WDT, there are three methods to be adopted, i.e.,
external reset (a low level to RES), software instruction,
and a ²HALT² instruction. There are two types of soft-
ware instructions; ²CLR WDT² and the other set - ²CLR
WDT1 ² and ²CLR WDT2². Of these two types of instruc-
tion, only one type of instruction can be active at a time
depending on the options - ²CLR WDT² times selection
option. If the ²CLR WDT² is selected (i.e., CLR WDT
times equal one), any execution of the ²CLR WDT² in-
struction clears the WDT. In the case that ²CLR WDT1²
and ²CLR WDT2² are chosen (i.e., CLR WDT times
equal two), these two instructions have to be executed
to clear the WDT; otherwise, the WDT may reset the
chip due to time-out.
Multi-function timer
The HT49R70A-1 provides a multi-function timer for the
WDT , time base and RTC but with different time-out pe-
riods. The multi-function timer consists of an 8-stage di-
vider and a 7-bit prescaler, with the clock source coming
from the WDT OSC or RTC OSC or the instruction clock
(i.e.., system clock divided by 4). The multi-function
timer also provides a selectable frequency signal
(ranges from f
S
/2
2
to f
S
/2
8
) for LCD driver circuits, and a
selectable frequency signal (ranging from f
S
/2
2
to f
S
/2
9
)
for the buzzer output by options. It is recommended to
select a nearly 4kHz signal for the LCD driver circuits to
have proper display.
Time base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from f
S
/2 12 to f
S
/2 15 selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 14H occurs. The time base time-out signal can also
be applied as a clock source of the Timer/Event Counter
1 so as to get a longer time-out period.
S y s t e m C l o c k / 4
D i v i d e r
W D T C l e a r
R O M
C o d e
O p t i o n
W D T
O S C
1 2 k H z
R T C
O S C
3 2 7 6 8 H z
C K T
R
C K T
R
f S
T i m e - o u t R e s e t f S / 2 1 6
D i v i d e r
Watchdog Timer
f s
D i v i d e r P r e s c a l e r
R O M C o d e O p t i o n
L C D D r i v e r ( f S / 2 2 ~ f S / 2 8 )
B u z z e r ( f S / 2 2 ~ f S / 2 9 )
T i m e B a s e I n t e r r u p t
f
S / 2 1 2 ~ f S / 2 1 5
R O M
C o d e
O p t i o n
Time base