Rainbow Electronics AT49BV512 - Manual (Page 2)

2
AT49BV512
1026E–FLASH–06/02
the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typ-
ical byte programming time is a fast 30 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a reprogramming write lock out fea-
ture to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
reprogrammed.
Block Diagram
Device Operation
READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K
bytes if the boot block featured is used) must be erased. The erased state of the mem-
ory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte
software code. The software chip erase code consists of 6-byte load commands to spe-
cific address locations with a specific data pattern (please refer to the Chip Erase Cycle
Waveforms).
After the software chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has been enabled, the data in the
boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be pro-
grammed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is
accomplished via the internal device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The device will automatically generate
the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified t
BP
cycle time. The DATA polling feature
may also be used to indicate the end of a program cycle.
DATA INPUTS/OUTPUTS
I/O0 - I/O7
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(56K BYTES)
OPTIONAL BOOT
BLOCK (8K BYTES)
OE, CE AND WE
LOGIC
Y DECODER
X DECODER
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
1FFFH
2000H
FFFFH
0000H