Document Outline

• Features
• Features (Continued)
• Pin Configurations
  • Disclaimer
• Overview
  • Block Diagram
  • Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490
  • Pin Descriptions
    • VCC
    • GND
    • Port A (PA7..PA0)
    • Port B (PB7..PB0)
    • Port C (PC7..PC0)
    • Port D (PD7..PD0)
    • Port E (PE7..PE0)
    • Port F (PF7..PF0)
    • Port G (PG5..PG0)
    • Port H (PH7..PH0)
    • Port J (PJ6..PJ0)
    • RESET
    • XTAL1
    • XTAL2
    • AVCC
    • AREF
    • LCDCAP
• Resources
• About Code Examples
• AVR CPU Core
  • Introduction
  • Architectural Overview
  • ALU - Arithmetic Logic Unit
  • AVR Status Register
    • SREG - AVR Status Register
  • General Purpose Register File
    • The X-register, Y-register, and Z-register
  • Stack Pointer
  • Instruction Execution Timing
  • Reset and Interrupt Handling
    • Interrupt Response Time
• AVR ATmega329/3290/649/6490 Memories
  • In-System Reprogrammable Flash Program Memory
  • SRAM Data Memory
    • Data Memory Access Times
  • EEPROM Data Memory
    • EEPROM Read/Write Access
    • EEARH and EEARL - The EEPROM Address Register
    • EEDR - The EEPROM Data Register
    • EECR - The EEPROM Control Register
    • EEPROM Write During Power- down Sleep Mode
    • Preventing EEPROM Corruption
  • I/O Memory
    • General Purpose I/O Registers
    • GPIOR2 - General Purpose I/O Register 2
    • GPIOR1 - General Purpose I/O Register 1
    • GPIOR0 - General Purpose I/O Register 0
• System Clock and Clock Options
  • Clock Systems and their Distribution
    • CPU Clock - clkCPU
    • I/O Clock - clkI/O
    • Flash Clock - clkFLASH
    • Asynchronous Timer Clock - clkASY
    • ADC Clock - clkADC
  • Clock Sources
  • Default Clock Source
  • Crystal Oscillator
  • Low-frequency Crystal Oscillator
  • Calibrated Internal RC Oscillator
    • OSCCAL - Oscillator Calibration Register
  • External Clock
  • Clock Output Buffer
  • Timer/Counter Oscillator
  • System Clock Prescaler
    • CLKPR - Clock Prescale Register
    • Switching Time
• Power Management and Sleep Modes
  • Idle Mode
  • ADC Noise Reduction Mode
  • Power-down Mode
  • Power-save Mode
  • Standby Mode
  • Power Reduction Register
  • Minimizing Power Consumption
    • Analog to Digital Converter
    • Analog Comparator
    • Brown-out Detector
    • Internal Voltage Reference
    • Watchdog Timer
    • Port Pins
    • JTAG Interface and On-chip Debug System
  • Register Description
    • SMCR - Sleep Mode Control Register
    • PRR - Power Reduction Register
• System Control and Reset
  • Resetting the AVR
  • Reset Sources
  • Power-on Reset
  • External Reset
  • Brown-out Detection
  • Watchdog Reset
  • MCUSR - MCU Status Register
  • Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
  • Watchdog Timer
    • WDTCR - Watchdog Timer Control Register
  • Timed Sequences for Changing the Configuration of the Watchdog Timer
    • Safety Level 1
    • Safety Level 2
• Interrupts
  • Interrupt Vectors in ATmega329/3290/649/6490
    • Moving Interrupts Between Application and Boot Space
    • MCUCR - MCU Control Register
• External Interrupts
  • Pin Change Interrupt Timing
    • EICRA - External Interrupt Control Register A
    • External Interrupt Mask Register - EIMSK
    • EIFR - External Interrupt Flag Register
    • PCMSK3 - Pin Change Mask Register 3(1)
    • PCMSK2 - Pin Change Mask Register 2(1)
    • PCMSK1 - Pin Change Mask Register 1
    • PCMSK0 - Pin Change Mask Register 0
• I/O-Ports
  • Introduction
  • Ports as General Digital I/O
    • Configuring the Pin
    • Toggling the Pin
    • Switching Between Input and Output
    • Reading the Pin Value
    • Digital Input Enable and Sleep Modes
    • Unconnected Pins
  • Alternate Port Functions
    • MCUCR - MCU Control Register
    • Alternate Functions of Port A
    • Alternate Functions of Port B
    • Alternate Functions of Port C
    • Alternate Functions of Port D
    • Alternate Functions of Port E
    • Alternate Functions of Port F
    • Alternate Functions of Port G
    • Alternate Functions of Port H
    • Alternate Functions of Port J
  • Register Description for I/O-Ports
    • PORTA - Port A Data Register
    • DDRA - Port A Data Direction Register
    • PINA - Port A Input Pins Address
    • PORTB - Port B Data Register
    • DDRB - Port B Data Direction Register
    • PINB - Port B Input Pins Address
    • PORTC - Port C Data Register
    • DDRC - Port C Data Direction Register
    • PINC - Port C Input Pins Address
    • PORTD - Port D Data Register
    • DDRD - Port D Data Direction Register
    • PIND - Port D Input Pins Address
    • PORTE - Port E Data Register
    • DDRE - Port E Data Direction Register
    • PINE - Port E Input Pins Address
    • PORTF - Port F Data Register
    • DDRF - Port F Data Direction Register
    • PINF - Port F Input Pins Address
    • PORTG - Port G Data Register
    • DDRG - Port G Data Direction Register
    • PING - Port G Input Pins Address
    • PORTH - Port H Data Register(1)
    • DDRH - Port H Data Direction Register(1)
    • PINH - Port H Input Pins Address(1)
    • PORTJ - Port J Data Register(1)
    • DDRJ - Port J Data Direction Register(1)
    • PINJ - Port J Input Pins Address(1)
• 8-bit Timer/Counter0 with PWM
  • Overview
    • Registers
    • Definitions
  • Timer/Counter Clock Sources
  • Counter Unit
  • Output Compare Unit
    • Force Output Compare
    • Compare Match Blocking by TCNT0 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 8-bit Timer/Counter Register Description
    • TCCR0A - Timer/Counter Control Register A
    • TCNT0 - Timer/Counter Register
    • OCR0A - Output Compare Register A
    • TIMSK0 - Timer/Counter 0 Interrupt Mask Register
    • TIFR0 - Timer/Counter 0 Interrupt Flag Register
• Timer/Counter0 and Timer/Counter1 Prescalers
  • Internal Clock Source
  • Prescaler Reset
  • External Clock Source
  • GTCCR - General Timer/Counter Control Register
• 16-bit Timer/Counter1
  • Overview
    • Registers
    • Definitions
    • Compatibility
  • Accessing 16-bit Registers
    • Reusing the Temporary High Byte Register
  • Timer/Counter Clock Sources
  • Counter Unit
  • Input Capture Unit
    • Input Capture Trigger Source
    • Noise Canceler
    • Using the Input Capture Unit
  • Output Compare Units
    • Force Output Compare
    • Compare Match Blocking by TCNT1 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
    • Phase and Frequency Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 16-bit Timer/Counter Register Description
    • TCCR1A - Timer/Counter1 Control Register A
    • TCCR1B - Timer/Counter1 Control Register B
    • TCCR1C - Timer/Counter1 Control Register C
    • TCNT1H and TCNT1L - Timer/Counter1
    • OCR1AH and OCR1AL - Output Compare Register 1 A
    • OCR1BH and OCR1BL - Output Compare Register 1 B
    • ICR1H and ICR1L - Input Capture Register 1
    • TIMSK1 - Timer/Counter1 Interrupt Mask Register
    • TIFR1 - Timer/Counter1 Interrupt Flag Register
• 8-bit Timer/Counter2 with PWM and Asynchronous Operation
  • Overview
    • Registers
    • Definitions
  • Timer/Counter Clock Sources
  • Counter Unit
  • Output Compare Unit
    • Force Output Compare
    • Compare Match Blocking by TCNT2 Write
    • Using the Output Compare Unit
  • Compare Match Output Unit
    • Compare Output Mode and Waveform Generation
  • Modes of Operation
    • Normal Mode
    • Clear Timer on Compare Match (CTC) Mode
    • Fast PWM Mode
    • Phase Correct PWM Mode
  • Timer/Counter Timing Diagrams
  • 8-bit Timer/Counter Register Description
    • TCCR2A - Timer/Counter Control Register A
    • TCNT2 - Timer/Counter Register
    • OCR2A - Output Compare Register A
  • Asynchronous operation of the Timer/Counter
    • ASSR - Asynchronous Status Register
    • Asynchronous Operation of Timer/Counter2
    • TIMSK2 - Timer/Counter2 Interrupt Mask Register
    • TIFR2 - Timer/Counter2 Interrupt Flag Register
  • Timer/Counter Prescaler
    • GTCCR - General Timer/Counter Control Register
• SPI - Serial Peripheral Interface
  • Overview
  • SS Pin Functionality
    • Slave Mode
    • Master Mode
    • SPCR - SPI Control Register
    • SPSR - SPI Status Register
    • SPDR - SPI Data Register
  • Data Modes
• USART0
  • Overview
    • AVR USART vs. AVR UART - Compatibility
  • Clock Generation
    • Internal Clock Generation - The Baud Rate Generator
    • Double Speed Operation (U2Xn)
    • External Clock
    • Synchronous Clock Operation
  • Frame Formats
    • Parity Bit Calculation
  • USART Initialization
  • Data Transmission - The USART Transmitter
    • Sending Frames with 5 to 8 Data Bit
    • Sending Frames with 9 Data Bit
    • Transmitter Flags and Interrupts
    • Parity Generator
    • Disabling the Transmitter
  • Data Reception - The USART Receiver
    • Receiving Frames with 5 to 8 Data Bits
    • Receiving Frames with 9 Data Bits
    • Receive Compete Flag and Interrupt
    • Receiver Error Flags
    • Parity Checker
    • Disabling the Receiver
    • Flushing the Receive Buffer
  • Asynchronous Data Reception
    • Asynchronous Clock Recovery
    • Asynchronous Data Recovery
    • Asynchronous Operational Range
  • Multi-processor Communication Mode
    • Using MPCM
  • USART Register Description
    • UDRn - USART I/O Data Register n
    • UCSRnA - USART Control and Status Register n A
    • UCSRnB - USART Control and Status Register n B
    • UCSRnC - USART Control and Status Register n C
    • UBRRnL and UBRRnH - USART Baud Rate Registers n
  • Examples of Baud Rate Setting
• USI - Universal Serial Interface
  • Overview
  • Functional Descriptions
    • Three-wire Mode
    • SPI Master Operation Example
    • SPI Slave Operation Example
    • Two-wire Mode
    • Start Condition Detector
    • Clock speed considerations.
  • Alternative USI Usage
    • Half-duplex Asynchronous Data Transfer
    • 4-bit Counter
    • 12-bit Timer/Counter
    • Edge Triggered External Interrupt
    • Software Interrupt
  • USI Register Descriptions
    • USIDR - USI Data Register
    • USISR - USI Status Register
    • USICR - USI Control Register
• Analog Comparator
  • Overview
    • ADCSRB - ADC Control and Status Register B
    • ACSR - Analog Comparator Control and Status Register
  • Analog Comparator Multiplexed Input
    • DIDR1 - Digital Input Disable Register 1
• Analog to Digital Converter
  • Features
  • Operation
  • Starting a Conversion
  • Prescaling and Conversion Timing
  • Changing Channel or Reference Selection
    • ADC Input Channels
    • ADC Voltage Reference
  • ADC Noise Canceler
    • Analog Input Circuitry
    • Analog Noise Canceling Techniques
    • ADC Accuracy Definitions
  • ADC Conversion Result
    • ADMUX - ADC Multiplexer Selection Register
    • ADCSRA - ADC Control and Status Register A
    • ADCL and ADCH - The ADC Data Register
      • ADLAR = 0
      • ADLAR = 1
    • ADCSRB - ADC Control and Status Register B
    • DIDR0 - Digital Input Disable Register 0
• LCD Controller
  • Features
  • Overview
    • Definitions
    • LCD Clock Sources
    • LCD Prescaler
    • LCD Memory
    • LCD Contrast Controller/Power Supply
    • LCDCAP
    • LCD Buffer Driver
    • Display requirements
    • Minimizing power consumption
  • Mode of Operation
    • Static Duty and Bias
    • 1/2 Duty and 1/2 Bias
    • 1/3 Duty and 1/3 Bias
    • 1/4 Duty and 1/3 Bias
    • Low Power Waveform
    • Operation in Sleep Mode
    • Display Blanking
    • Port Mask
  • LCD Usage
    • LCD Initialization
    • Updating the LCD
    • Disabling the LCD
    • LCDCRA - LCD Control and Status Register A
    • LCDCRB - LCD Control and Status Register B
    • LCDFRR - LCD Frame Rate Register
    • LCDCCR - LCD Contrast Control Register
    • LCD Memory Mapping
• JTAG Interface and On-chip Debug System
  • Features
  • Overview
  • Test Access Port - TAP
  • TAP Controller
  • Using the Boundary- scan Chain
  • Using the On-chip Debug System
  • On-chip Debug Specific JTAG Instructions
    • PRIVATE0; 0x8
    • PRIVATE1; 0x9
    • PRIVATE2; 0xA
    • PRIVATE3; 0xB
  • On-chip Debug Related Register in I/O Memory
    • OCDR - On-chip Debug Register
  • Using the JTAG Programming Capabilities
  • Bibliography
• IEEE 1149.1 (JTAG) Boundary-scan
  • Features
  • System Overview
  • Data Registers
    • Bypass Register
    • Device Identification Register
      • Version
      • Part Number
      • Manufacturer ID
    • Reset Register
    • Boundary-scan Chain
  • Boundary-scan Specific JTAG Instructions
    • EXTEST; 0x0
    • IDCODE; 0x1
    • SAMPLE_PRELOAD; 0x2
    • AVR_RESET; 0xC
    • BYPASS; 0xF
  • Boundary-scan Related Register in I/O Memory
    • MCUCR - MCU Control Register
    • MCUSR - MCU Status Register
  • Boundary-scan Chain
    • Scanning the Digital Port Pins
    • Scanning the RESET Pin
    • Scanning the Clock Pins
    • Scanning the Analog Comparator
    • Scanning the ADC
  • ATmega329/3290/649/6490 Boundary-scan Order
  • Boundary-scan Description Language Files
• Boot Loader Support - Read-While-Write Self-Programming
  • Boot Loader Features
  • Application and Boot Loader Flash Sections
    • Application Section
    • BLS - Boot Loader Section
  • Read-While-Write and No Read-While-Write Flash Sections
    • RWW - Read-While-Write Section
    • NRWW - No Read-While-Write Section
  • Boot Loader Lock Bits
  • Entering the Boot Loader Program
    • SPMCSR - Store Program Memory Control and Status Register
  • Addressing the Flash During Self- Programming
  • Self-Programming the Flash
    • Performing Page Erase by SPM
    • Filling the Temporary Buffer (Page Loading)
    • Performing a Page Write
    • Using the SPM Interrupt
    • Consideration While Updating BLS
    • Prevent Reading the RWW Section During Self- Programming
    • Setting the Boot Loader Lock Bits by SPM
    • EEPROM Write Prevents Writing to SPMCSR
    • Reading the Fuse and Lock Bits from Software
    • Preventing Flash Corruption
    • Programming Time for Flash when Using SPM
    • Simple Assembly Code Example for a Boot Loader
    • ATmega329/3290/649/6490 Boot Loader Parameters
• Memory Programming
  • Program And Data Memory Lock Bits
  • Fuse Bits
    • Latching of Fuses
  • Signature Bytes
  • Calibration Byte
  • Parallel Programming Parameters, Pin Mapping, and Commands
    • Signal Names
  • Parallel Programming
    • Enter Programming Mode
    • Considerations for Efficient Programming
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Low Bits
    • Programming the Fuse High Bits
    • Programming the Extended Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
    • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Pin Mapping
    • Serial Programming Algorithm
    • Serial Programming Instruction set
    • SPI Serial Programming Characteristics
  • Programming via the JTAG Interface
    • Programming Specific JTAG Instructions
    • AVR_RESET (0xC)
    • PROG_ENABLE (0x4)
    • PROG_COMMANDS (0x5)
    • PROG_PAGELOAD (0x6)
    • PROG_PAGEREAD (0x7)
    • Data Registers
    • Reset Register
    • Programming Enable Register
    • Programming Command Register
    • Flash Data Byte Register
    • Programming Algorithm
    • Entering Programming Mode
    • Leaving Programming Mode
    • Performing Chip Erase
    • Programming the Flash
    • Reading the Flash
    • Programming the EEPROM
    • Reading the EEPROM
    • Programming the Fuses
    • Programming the Lock Bits
    • Reading the Fuses and Lock Bits
    • Reading the Signature Bytes
    • Reading the Calibration Byte
• Electrical Characteristics
  • Absolute Maximum Ratings*
  • DC Characteristics
  • External Clock Drive Waveforms
  • External Clock Drive
  • Maximum Speed vs. VCC
  • SPI Timing Characteristics
  • ADC Characteristics - Preliminary Data
  • LCD Controller Characteristics - Preliminary Data - TBD
  • Calibrated Internal RC Oscillator Accuracy
• ATmega329/3290/649/6490 Typical Characteristics - Preliminary Data
  • Active Supply Current
  • Idle Supply Current
  • Supply Current of I/O modules
    • Example
  • Power-down Supply Current
  • Power-save Supply Current
  • Standby Supply Current
  • Pin Pull-up
  • Pin Driver Strength
  • Pin Thresholds and hysteresis
  • BOD Thresholds and Analog Comparator Offset
  • Internal Oscillator Speed
  • Current Consumption of Peripheral Units
  • Current Consumption in Reset and Reset Pulsewidth
• Register Summary
• Instruction Set Summary
• Ordering Information
  • ATmega329
  • ATmega3290
  • ATmega649
  • ATmega6490
• Packaging Information
  • 64A
  • 64M1
  • 100A
• Errata
  • ATmega329 rev. C
  • ATmega329 rev. B
  • ATmega329 rev. A
  • ATmega3290 rev. C
  • ATmega3290 rev. B
  • ATmega3290 rev. A
  • ATmega649 rev. A
  • ATmega6490 rev. A
• Datasheet Revision History
  • Rev. 2552H - 11/06
  • Rev. 2552G - 07/06
  • Rev. 2552F - 06/06
  • Rev. 2552E - 04/06
  • Rev. 2552D - 03/06
  • Rev. 2552C - 03/06
  • Rev. 2552B - 05/05
  • Rev. 2552A -11/04
• Table of Contents