Rainbow Electronics ISD5100 - Manual (Page 72)

ISD5100 – SERIES
- 72 -
10.5. I 2 C P ROTOCOL
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit
that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master. For example, the valid Slave Addresses for the ISD5100 Series device, for both Write and
Read cycles, are shown in
section 7.3.1 on page 13 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1
st byte following the
Start Condition sequence. An example of a Master transmitting an address to a ISD5100 Series slave
is shown below. In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits. The following example details the transfer explained in
section 7.3.1 - 2 - 3 on pages 13-20 of this
datasheet .
Master Transmits to Slave Receiver (Write) Mode
S W A A A A P SLAVE ADDRESS COMMAND BYTE High ADDR. BYTE Low ADDR. BYTE
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
Start Bit Stop Bit
A common procedure in the ISD5100 Series is the reading of the Status Bytes. The Read Status
condition in the ISD5100 Series is triggered when the Master addresses the chip with its proper Slave
Address, immediately followed by the R/W bit set to a “1” and without the Command Byte being sent.
This is an example of the Master sending to the Slave, immediately followed by the Slave sending
data back to the Master. The “N” not-acknowledge cycle from the Master ends the transfer of data
from the Slave. The following example details the transfer explained in
section 7.3.1 on page 13 of this
datasheet.