Rainbow Electronics MAX1813 User Manual
Page 23
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
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23
from one clock frequency to another, the CPU first goes
into a low-power state, then the output voltage and
clock frequency are changed. The change must be
accomplished in 100µs or the system may halt.
At the beginning of an output voltage transition, the
MAX1813 forces the PGOOD output high. PGOOD
remains masked high until the slew-rate controller has
set the internal DAC to the final value and one addition-
al slew-rate clock period has passed.
The output voltage transition is performed in 25mV
increments, preceded by a 4µs delay and followed by
one additional clock period after which PGOOD will
remain high if the output voltage is in regulation. The
total time for a transition depends on R
TIME
, the voltage
difference, and the accuracy of the MAX1813’s slew-
rate clock. The greater the output capacitance, the
higher the surge current required for the transition. The
MAX1813 will automatically control the current to the
minimum level required to complete the transition in the
calculated time, as long as the surge current is less
than the current limit set by ILIM. The transition time is
given by:
where ƒ
SLEW
= 150kHz x 120k
Ω/R
TIME
, V
OLD
is the
original output voltage, and V
NEW
is the new output
voltage. See TIME Frequency Accuracy in Electrical
Characteristics for ƒ
SLEW
accuracy.
The practical range of R
TIME
is 47k
Ω to 470kΩ, corre-
sponding to 2.6µs to 26µs per 25mV step. Although the
DAC takes discrete 25mV steps, the output filter makes
the transitions relatively smooth. The average inductor
current required to make an output voltage transition is:
Power-On Reset and Undervoltage
Lockout
V
CC
undervoltage lockout (UVLO) circuitry inhibits
switching, forces PGOOD low, and forces the DL gate
driver high. If the V
CC
voltage drops below 4.2V, it is
assumed that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, DL is forced high in this mode; this will
force the output to ground. This results in large nega-
tive inductor current and possibly small negative output
voltages. If V
CC
is likely to drop in this fashion, the out-
put can be clamped with a Schottky diode to PGND to
reduce the negative excursion.
Power-on reset (POR) occurs when V
CC
rises above
approximately 2V. This resets the fault latch and pre-
pares the PWM for operation. When V
CC
rises above
4.2V, the DAC inputs are sampled, and the output volt-
age begins to slew to the DAC setting. To ensure cor-
rect startup, V+ should be present before V
CC
. If the
converter attempts to bring the output into regulation
without V+ present, the fault latch will trip. For automat-
ic startup, the battery voltage (V+) should be present
before V
CC
. The SKP/SDN pin can be forced low or
V
CC
power cycled to reset the fault latch.
Power-Good Output (PGOOD)
PGOOD is the open-drain output of a window compara-
tor. This power-good output remains high impedance
as long as the output voltage is within +10%/-12.5% of
the regulation voltage. When the output voltage is
greater than 10% or less than the -12.5% window limits,
the internal MOSFET is activated and pulls the output
low. While the slew-rate controller is active (except dur-
ing startup and shutdown), the MAX1813 forces
PGOOD high. PGOOD is low in shutdown, input under-
voltage lockout, and during startup. Any fault condition
forces PGOOD low until the fault is cleared. For logic-
level output voltages, connect an external pullup resis-
tor between PGOOD and V
CC
(or V
DD
). A 100k
Ω
resistor works well in most applications.
I
C
25mV
L
OUT
SLEW
≅
Ч
Ч ƒ
t
4 s +
1
1+
V
- V
25mV
TRAN
SLEW
OLD
NEW
≤ µ
ƒ
26k
Ω
D4
D3
D2
D1
D0
26k
Ω
26k
Ω
26k
Ω
26k
Ω
8k
Ω
100k
Ω
8k
Ω
8k
Ω
8k
Ω
8k
Ω
3.0V TO 5.5V
100k
Ω
+5V
B-DATA
LATCH
V
CC
GND
MAX1813
Figure 7. Internal Mux Impedance-Mode Data Test and Latch