Rainbow Electronics MAX1545 User Manual
Page 33
MAX1519/MAX1545
Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
______________________________________________________________________________________
33
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For 3- or 4-
phase operation, the maximum ESR to meet ripple
requirements is:
where
η
TOTAL
is the total number of active phases, t
ON
is the calculated on-time per phase, and t
TRIG
is the
trigger delay between the master’s DH rising edge and
the slave’s DH rising edge. The trigger delay must be
less than 1/(f
SW
× η
TOTAL
) for stable operation. The
actual capacitance value required relates to the physi-
cal size needed to achieve low ESR, as well as to the
chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of polymer
types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SAG
and V
SOAR
from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the V
SAG
and V
SOAR
equations
in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
where:
and:
where C
OUT
is the total output capacitance, R
ESR
is the
total equivalent-series resistance, R
SENSE
is the cur-
rent-sense resistance, A
VPS
is the voltage-positioning
gain, and R
PCB
is the parasitic board resistance
between the output capacitors and sense resistors.
For a standard 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum, Sanyo POSCAP, and Panasonic SP capacitors
in widespread use at the time of publication have typical
ESR zero frequencies below 50kHz. For example, the
ESR needed to support a 30mV
P-P
ripple in a 40A design
is 30mV/(40A
× 0.3) = 2.5mΩ. Four 330µF/2.5V Panasonic
SP (type XR) capacitors in parallel provide 2.5m
Ω (max)
ESR. Their typical combined ESR results in a zero at
40kHz.
Ceramic capacitors have a high ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the out-
put without verifying that the circuit contains enough
voltage positioning and series PC board resistance to
ensure stability. When only using ceramic output
capacitors, output overshoot (V
SOAR
) typically deter-
mines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load con-
ditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
The efficiency penalty for operating at 550kHz is about
5% when compared to the 300kHz circuit, primarily due
to the high-side MOSFET switching losses.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double-pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
R
R
A
R
R
EFF
ESR
VPS SENSE
PCB
=
+
+
f
R
C
ESR
EFF
OUT
=
1
2
π
f
f
ESR
SW
≤
π
R
V
L
V
V
t
V
t
ESR
RIPPLE
IN
TOTAL OUT ON
TOTAL OUT TRIG
≤
−
−
(
)
2
η
η