Table 29. spdt2 switch control configuration, Table 30. apio_ mode bit configuration – Rainbow Electronics MAX1329 User Manual

Page 57

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MAX1329/MAX1330

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,

Reference, Voltage Monitors, and Temp Sensor

______________________________________________________________________________________

57

APIO Control Register

The Analog Programmable Input/Output (APIO) Control
register configures the modes of APIO1–APIO4.
APIO1–APIO4 I/O logic levels are referenced to AV

DD

and

AGND (see Analog I/O in the

Electrical Characteristics

table). APIO_ is configurable as a general-purpose input,

active-low wake-up input, general-purpose output, or seri-
al-interface, level-shifted buffered I/O.

AP_MD<1:0>: APIO_ Mode Configuration bits (default
= 00). AP_MD<1:0> configures the APIO_ mode
according to Table 30.

MSB

LSB

NAME

AP4MD1

AP4MD0

AP3MD1

AP3MD0

AP2MD1

AP2MD0

AP1MD1

AP1MD0

DEFAULT

0

0

0

0

0

0

0

0

Table 29. SPDT2 Switch Control Configuration

SPDT2 SWITCH STATE

SPDT21

BIT

SPDT20

BIT

DPIO4

DPIO3

DPIO2

DPIO1

SNO2-TO-SCM2 STATE

SNC2-TO-SCM2 STATE

0

0

0

0

0

0

Open

Open

0

X

X

X

X

1

Closed

Closed

0

X

X

X

1

X

Closed

Closed

0

X

X

1

X

X

Closed

Closed

0

X

1

X

X

X

Closed

Closed

0

1

X

X

X

X

Closed

Closed

1

0

0

0

0

0

Open

Closed

1

X

X

X

X

1

Closed

Open

1

X

X

X

1

X

Closed

Open

1

X

X

1

X

X

Closed

Open

1

X

1

X

X

X

Closed

Open

1

1

X

X

X

X

Closed

Open

Table 30. APIO_ Mode Bit Configuration

AP_MD1

AP_MD0

MODE

DESCRIPTION

0

0

GPI

Digital input. APIO_ logic level read from AP_LL register bit.

0

1

WUL

Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator.

1

0

GPO

Digital output. Set the APIO_ logic level by writing to the AP_LL register bit.

1

1

SPI

Digital input or output. The SPI mode functions differ for each APIO1–APIO4.

• APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and

APIO1 is a GPI, when

CS is low. Set the resistor pullup configuration with the

AP1PU bit.

• APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and

becomes a GPO with the level set by AP2LL bit when

CS is low.

• APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and

becomes a GPO with the level set by the AP3LL bit when

CS is low.

• APIO4 digital output. APIO4 inverts and then outputs the CS logic level.

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