Rainbow Electronics MAX1329 User Manual
Page 61
MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
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61
MSB
NAME
VM1A
VM1B
VM2
ADD
AFF
ACF
GTA
LTA
DEFAULT
0*
0*
0
0
0
0
0
0
NAME
APR4
APR3
APR2
APR1
APF4
APF3
APF2
APF1
DEFAULT
0
0
0
0
0
0
0
0
LSB
NAME
DPR4
DPR3
DPR2
DPR1
DPF4
DPF3
DPF2
DPF1
DEFAULT
0
0
0
0
0
0
0
0
*
The default states for VM1A and VM1B are 0. However, at power-up, the voltage monitor asserts VM1A and VM1B.
GTA: ADC Greater-Than (GT) Alarm Status bit (default
= 0). GTA = 1 indicates that ADC GT alarm has been
tripped. The GTA bit clears to 0 by reading the Status
register or by writing the ADC GT Alarm register.
LTA: ADC Less-Than (LT) Alarm Status bit (default = 0).
LTA = 1 indicates that the ADC LT alarm has been
tripped. The LTA bit clears to 0 by reading the Status
register or by writing the ADC LT Alarm register.
APR<4:1>: APIO Rising-Edge Status bit (default = 0). A
logic-high in the APR<4:1> bits indicate that a rising
edge has been detected on the corresponding APIO_.
APR_ clears to 0 when the Status register is read.
APF<4:1>: APIO Falling-Edge Status bit (default = 0). A
logic-high in the APF<4:1> bits indicate that a falling
edge has been detected on the corresponding APIO_.
APF_ clears to 0 when the Status register is read.
DPR<4:1>: DPIO Rising-Edge Status bit (default = 0). A
logic-high in the DPR<4:1> bits indicate that a rising
edge has been detected on the corresponding DPIO_.
DPR_ clears to 0 when the Status register is read.
DPF<4:1>: DPIO Falling-Edge Status bit (default = 0). A
logic-high in the DPF<4:1> bits indicate that a falling
edge has been detected on the corresponding DPIO_.
DPF_ clears to 0 when the Status register is read.