Application information – Diodes ZXLD1356/ ZXLD1356Q User Manual

Page 20

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ZXLD1356/ ZXLD1356Q

Document number: DS33470 Rev. 4 - 2

20 of 29

www.diodes.com

October 2012

© Diodes Incorporated

ZXLD1356/ ZXLD1356Q

A Product Line of

Diodes Incorporated


Application Information

(cont.)

Driving the ADJ Input via Open Collector Transistor

The recommended method of driving the ADJ pin and controlling the amplitude of the PWM waveform is to use a small NPN switching transistor

as shown below:

PWM

GND

ZXLD1356

A DJ

GND

This scheme uses the 50k resistor between the ADJ pin and the internal voltage reference as a pull-up resistor for the external transistor eg

MMBT3904.

Driving the ADJ Input from a Microcontroller

Another possibility is to drive the device from the open drain output of a microcontroller. The diagram below shows one method of doing this:

GND

ZXLD1356

ADJ

MCU

3.3k

If the NMOS transistor within the microcontroller has high Gate / Drain capacitance, this arrangement can inject a negative spike into ADJ input

of the ZXLD1356 and cause erratic operation but the addition of a Schottky clamp diode (eg Diodes Inc. SD103CWS) to ground and inclusion of

a series resistor (3.3k) will prevent this. See the section on PWM dimming for more details of the various modes of control using high frequency

and low frequency PWM signals.

Shutdown Mode

Taking the ADJ pin to a voltage below 0.2V for more than approximately 100µs will turn off the output and supply current to a low standby level of

65µA nominal.

Note that the ADJ pin is not a logic input. Taking the ADJ pin to a voltage above V

REF

will increase output current above the 100% nominal

average value. (See page 17 graphs for details).

Soft-Start

An external capacitor from the ADJ pin to ground will provide a soft-start delay, by increasing the time taken for the voltage on this pin to rise to

the turn-on threshold and by slowing down the rate of rise of the control voltage at the input of the comparator. Adding capacitance increases this

delay by approximately 0.2ms/nF. The graph on the next page shows the variation of soft-start time for different values of capacitor.

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