Diodes ZNBG3116 - Manual (Page 10)

ZNBG3115
ZNBG3116
ISSUE 2 - JUNE 2006
10
APPLICATIONS CIRCUIT
The diagrams below show partial application circuits for the ZNBG series showing all external components
required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with
the associated FETs and gate and drain capacitors in circuit.
To minimise board space the ZNBG3115/3116 is offered in a QSOP16 package. To reduce the pin count Drain 1
and Drain 2 have been internally connected. This is possible because only one of the two bias stages can biased at
one time.The QSOP16 offers a 40% reduction in size over the QSOP20 version.
Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect
other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF
feedthrough between stages via the ZNBG device. These capacitors are required for all stages used. Values of
10nF and 4.7nF respectively are
recommended however this is design
dependent and any value between 1nF
and 100nF could be used.
The capacitors C
NB
and C
SUB
are an
integral part of the ZNBGs negative
supply generator. The negative bias
voltage is generated on-chip using an
internal oscillator. The required value
of capacitors C
NB
and C
SUB
is 47nF.
This generator produces a low current
supply of approximately -3 volts.
Although this generator is intended
purely to bias the external FETs, it can
be used to power other external
circuits via the C
SUB
pin.
Resistor R
CAL
sets the drain current at
which all external FETs are operated. If
any bias control circuit is not required,
its related drain and gate connections
may be left open circuit without
a f f e c t i n g t h e o p e r a t i o n o f t h e
remaining bias circuits.
T h e Z N B G d e v i c e s h a v e b e e n
designed to protect the external FETs
from adverse operating conditions.
With a JFET connected to any bias
circuit, the gate output voltage of the
bias circuit can not exceed the range
-3.0V to 1V under any conditions,
including powerup and powerdown
transients. All the bias stages include
drain currents limits which work
independently in each stage. Should
the negative bias generator be shorted
or overloaded so that the drain current
of the external FETs can no longer be
controlled, the drain supply to FETs is
shut down to avoid damage to the
FETs by excessive drain current.
QSOP16 Applications circuit
QSOP20 Applications circuit